Blackfin Embedded Processor with 16 Mbits Flash memory and RSI
The ADSP-BF514F16 products have been introduced to replace the now obsolete ADSP-BF51xF products. The processors are completely code compatible with other Blackfin processors.
By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances.
The ADSP-BF51x processors are highly integrated system-on-achip solutions for the next generation of embedded network connected applications. By combining industry-standard interfaces with a high performance signal processing core, costeffective applications can be developed quickly, without the need for costly external components. The system peripherals include an IEEE-compliant 802.3 10/100 Ethernet MAC with IEEE-1588 support (ADSP-BF518/ADSP-BF518F16 only), an RSI controller, a TWI controller, two UART ports, two SPI ports, two serial ports (SPORTs), nine general-purpose 32-bit timers (eight with PWM capability), 3-phase PWM for motor control, a real-time clock, a watchdog timer, and a parallel peripheral interface (PPI).
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. The compare/select and vector search instructions are also provided.
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
New debug feature added for the ICE-1000/ICE-2000:
- Coresight Serial Wire Debug (SWD)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
- 13 week(s) ago in Blackfin Processors
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