Documentation Errata for ADSP-BF50x Blackfin ® Processor Hardware Reference

Chapter: 10 / Page 3

Doc ID: DOC-1421

Change

In the section External Interface, the clock value should be changed from 133 MHz to 100 Mhz as follows:

When clocked internally, the clock source is the processor’s peripheral clock (SCLK). Assuming the peripheral clock is running at 100 MHz, the maximum period for the timer count is ((232-1) / 100 MHz) = 43 seconds.

Chapter: 13 / Page 8

Doc ID: DOC-1422

Change

In the section Input Noise Filtering (Debouncing), the clock value should be changed from 133 MHz to 100 MHz, and the equations for filter time range should be changed as follows:

Assuming an SCLK frequency of 100 MHz, the filter time range is shown by the following equations:

DPRESCALE = 0b0000
          tfilter = 128*1*10ns = 1.28µs

DPRESCALE = 0b10001
          tfilter = 128*(131072)*10ns = 167772us = (approx.) 168ms

Chapter: 15 / Page 19

Doc ID: DOC-1417

Change

In the section Bit Rate Generation, change the title for Table 15-2 to UART Bit Rate Examples With 100 MHz SCLK, and replace the table as follows:

Bit
Rate
Dfactor = 16Dfactor = 1
DLActual%ErrorDLActual%Error
240026042400.150.006416672399.980.001
480013024800.310.006208334800.080.002
96006519600.610.006104179599.690.003
1920032619171.780.147520819201.230.006
3840016338343.560.147260438402.460.006
5760010957339.450.452173657603.690.006
11520054115740.740.469868115207.370.006
9216007892857.143.119109917431.190.452
150000041562500.004.167671492537.310.498
300000023125000.004.167333030303.031.010
625000016250000.000.000166250000.000.000

Chapter: 16 / Page 4

Doc ID: DOC-1423

Change

In the section Serial Clock Signal (SCL), the clock value should be changed from 133 MHz to 83 MHz, and the example should be changed as follows:

Note: It is not always possible to achieve 10 MHz accuracy. In such cases, it is safe to round up the PRESCALE value to the next highest integer. For example, if SCLK is 83 MHz, the PRESCALE value is calculated as 83 MHz/10 MHz = 8.3. In this case, a PRESCALE value of 9 ensures that all timing requirements are met.

Chapter: 18 / Page 45

Doc ID: DOC-1424

Change

In the section Code-Generated Transfer, the SCLK and SPI clock values in the comments to the SPI_Register_Initialization function in Listings 18-1 and 18-6 should be changed as follows:

SPI_Register_Initialization:
P0.H = hi(SPI_FLG);
P0.L = lo(SPI_FLG);
R0 = W[P0] (Z);
BITSET (R0,0x7); /* FLS7 */
W[P0] = R0; /* Enable slave-select output pin */

P0.H = hi(SPI_BAUD);
P0.L = lo(SPI_BAUD);
R0.L = 0x208E; /* Write to SPI Baud rate register */
W[P0] = R0.L; ssync; /* If SCLK = 100 MHz, SPI clock ~= 6 kHz
*/


Last Update Date: May 25 2017

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