Micro-PMU with 0.8 A Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset
The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes the board space.
The MODE pin selects the buck mode of operation. When set to logic high, the buck regulators operate in forced PWM mode. When the MODE pin is set to logic low, the buck regulators operate in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold the regulator operates in power save mode (PSM) improving the light-load efficiency.
The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5043 LDOs extend the battery life of portable devices. The LDO maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.
Each regulator is activated by a high level on the respective enable pin. The ADP5043 is available with factory programmable default output voltages and can be set to a wide range of options.
The ADP5043 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. They also provide power-on reset signals. An on-chip dual watchdog timer can reset the microprocessor or power cycle the system (Watchdog 2) if it fails to strobe within a preset timeout period.
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
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