Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or manually adjustable .
The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.
The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features.
The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.
- SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all
associated FEC rates
- 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE
- WDM transponders
- Any rate regenerators/repeaters
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The ADI-BERT reference circuit solution is a flexible, continuous rate pattern generator and error detector of up to 11.3 Gbps that enables test pattern generation for a wide range of industry protocols and data rates.
The ADN2915 clock and data recovery (CDR) IC runs any rate from 10 Mbps to 11.3 Gbps. For full details on the ADN2915, see the ADN2915 data sheet, which should be consulted in conjunction with the UG-551 when using this reference circuit.