Continuous Rate 6.5 Mbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
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Product Details

The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance.

The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or manually adjustable .

The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.

The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features.

The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.


  • SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all
    associated FEC rates
  • 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE
  • WDM transponders
  • Any rate regenerators/repeaters

Product Lifecycle

checked Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits

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Product Details

Test pattern generation and error detection are critical functions needed for design, development, and debug of systems with high speed serial interfaces.

The ADI-BERT reference circuit solution is a flexible, continuous rate pattern generator and error detector of up to 11.3 Gbps that enables test pattern generation for a wide range of industry protocols and data rates.

The ADN2915 clock and data recovery (CDR) IC runs any rate from 10 Mbps to 11.3 Gbps. For full details on the ADN2915, see the ADN2915 data sheet, which should be consulted in conjunction with the UG-551 when using this reference circuit.

Design Resources

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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

ADN2915 Material Declaration
PCN-PDN Information Quality And Reliability Symbols and Footprints



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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

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Evaluation Boards Pricing displayed is based on 1-piece.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.