Continuous Rate 10 Mbps to 2.7 Gbps Clock and Data Recovery IC (With High Sensitivity Limiting Amp)
This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, and low power fiber optic receiver.
The ADN2817/ADN2818 have many optional features available through an I2C® interface. For example, the user can read back the data rate onto which the ADN2817 or ADN2818 is locked, or the user can set the device to lock only to one particular data rate if provisioning of data rates is required. A BERMON circuit provides an estimate of the received bit error rate (BER) without interruption of the data. Alternatively, the user can adjust the data sampling phase to optimize the received BER.
The ADN2817/ADN2818 are available in a compact 5 mm × 5 mm, 32-lead, lead frame chip scale package.
Data Sheet, Rev. A, 8/08