Dual Rate Limiting Amplifier and Clock and Data Recovery IC
The proprietary delay and phase-locked loop design of the ADN2811 provides unprecedented jitter performance for robust high-speed networking designs.
The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip crystal oscillator. Both native rates and 15/14 rate digital wrappers rates are supported by the ADN2811, without any change of reference clock required. This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold.
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At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.