Low Cost LVDT-to-Digital Converter
The AD2S93 has a 16-bit serial output. The MSB (LOS), read first, indicates a loss of the signal A, B, or reference inputs to the converter or transducer. The second and third MSBs are flags indicating whether [–REF/2 (UNR) £ A–B £ +REF/2 (OVR]) is outside the linear operating range of the converter. The displacement data is presented as 13-bit offset binary giving a ±12-bit operating range. LOS, OVR and UNR are pinned out on the device, in addition a NULL flag is available which is set when (A–B) = 0.
Absolute displacement information is accessed when CS is taken LO followed by the application of an external clock (SCLK) with a maximum rate of 2 MHz. Data is read MSB first. When CS is high the DATA output is high impedance; this allows daisy chaining of more than one converter onto a common bus.
The A, B differential input allows the user to scale the A, B inputs between 1 and 10. This enables the user to accurately set up the inputs matching the REF input to the DIFF output. The DIFF output is the resultant A–B. The AD2S93 operates using ±5 V ± 5% power supplies and is fabricated on Analog Devices’ linear compatible CMOS process (LC2MOS). The (LC2MOS) is a mixed technology process that combines precision bipolar circuits with low power logic.