Dual High Speed PECL Comparator 16 - Lead QSOP
A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from -2.0 V to +3.0 V. Outputs are complementary digital signals that are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 . to VDD - 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation.
The ADCMP561/ADCMP562 are specified over the industrial temperature range (-40°C to +85°C). The ADCMP561 is available in a 16-lead QSOP package. The ADCMP562 is available in a 20-lead QSOP package.
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.