Dual High Speed PECL Comparator 16 - Lead QSOP
A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from -2.0 V to +3.0 V. Outputs are complementary digital signals that are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 . to VDD - 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation.
The ADCMP561/ADCMP562 are specified over the industrial temperature range (-40°C to +85°C). The ADCMP561 is available in a 16-lead QSOP package. The ADCMP562 is available in a 20-lead QSOP package.
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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