Programmable Low Voltage 1:10 LVDS Clock Driver
When the enable input EN is high, the device may be pro-grammed by clocking 11 data bits into the shift register. The first 10 bits determine which outputs are enabled (0 = disabled, 1 = enabled), while the 11th bit selects the clock input (0 = CLK0, 1 = CLK1). A 12th clock pulse transfers data from the shift register to the control register.
The ADN4670 is fully specified over the industrial temperature range and is available in a 32-lead LFCSP package.
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
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