3.3 V, 200 Mbps, Half-Duplex, High Speed M-LVDS Transceiver with Type 2 Receiver
The parts adhere to the TIA/EIA-899 standard for M-LVDS and are similar to counterpart LVDS devices that comply with the TIA/EIA-644 standard for LVDS, but designed with features for multipoint applications. These features include a driver output that supports multipoint bus loads as low as 30 Ω, with controlled transition times to permit stubs from the backbone transmission line. Up to 32 nodes can be connected to the bus.
The ADN4696E/ADN4697E are Type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle failsafe) or the inputs are open (open-circuit fail safe). The ADN4696E/ADN4697E is available as half-duplex configuration in an 8-lead SOIC package (ADN4696E) or as full-duplex configuration in 14-lead SOIC package (ADN4697E).
- Backplane and cable multipoint data transmission
- Multipoint clock distribution
- Low power, high-speed alternative to shorter RS-485 links
- Networking routers and switches
- Wireless base station infrastructure
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The EVAL-ADN469xEHDEBZ allows quick and easy evaluation of half-duplex M-LVDS transceivers (ADN4690E, ADN4691E, ADN4694E, ADN4696E). The evaluation board allows all of the input and output functions to be exercised without the need for external components. Screw terminal blocks provide convenient connections for power and ground, with SMB jack connectors for high-speed logic and M-LVDS bus signals.The evaluation board has an 8-lead SOIC footprint for a half-duplex M-LVDS transceiver from the ADN469xE family.