3 V LVDS Quad CMOS Differential Line Driver
The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typi- cally ±310 mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver, such as the ADN4668.
The ADN4667 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW.
The ADN4667 and its companion LVDS receiver, the ADN4668, offer a new solution to high speed, point-to-point data trans- mission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).
Data Sheet, Rev. A, 5/08
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