A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is manufactured on a 0.18 µm CMOS process and operates from 1.8 V and 3.3 V supplies for a total power consumption of 380 mW in bypass mode. It is supplied in a 160-lead chip scale ball grid array for reduced package parasitics.
- Low noise and intermodulation distortion (IMD) features enable high quality synthesis of wideband signals at intermediate frequencies up to 600 MHz.
- Double data rate (DDR) LVDS data receivers support the maximum conversion rate of 1200 MSPS.
- Direct pin programmability of basic functions or SPI port access offers complete control of all AD973x family functions.
- Manufactured on a CMOS process, the AD973x family uses a proprietary switching technique that enhances dynamic performance.
- The current output(s) of the AD9736 family are easily configured for single-ended or differential circuit topologies.
- Broadband communications systems
Cellular infrastructure (digital predistortion)
- Point-to-point wireless
- Instrumentation, automatic test equipment
- Radar, avionics
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