2.5V to 5.5V, 115µA Parallel Interface Single Voltage Output 12-Bit DAC
The AD5330/AD5331/AD5340/AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in thin shrink small outline packages (TSSOP).
* Protected by U.S. Patent Number 5,969,657; other patents pending.
Data Sheet, Rev. A, 2/08
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At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
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