PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs
The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider.
By connecting an external 25 MHz crystal, output frequencies of 100 MHz and 33.33 MHz can be locked to the input reference. The output divider and feedback divider ratios are prepro-grammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space.
The AD9573 is available in a 16-lead 4.4 mm × 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C.
- Line cards, switches, and routers
- CPU/PCIe applications
- Low jitter, low phase noise clock generation
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.