1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
The AD9510 provides a multi-output clock distribution function along with an on-chip phase-locked loop (PLL) core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this device.
The PLL section consists of a programmable reference divider (R); a low noise, phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external voltage-controlled crystal oscillator (VCXO) or voltage-controlled oscillator (VCO) to the CLK2 and CLK2B pins, frequencies of up to 1.6 GHz can be synchronized to the input reference.
There are eight independent clock outputs. Four outputs are low voltage positive emitter-coupled logic (LVPECL) at 1.2 GHz, and four are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a coarse timing adjustment. Two of the LVDS/CMOS outputs feature programmable delay elements with full-scale ranges up to 8 ns of delay. This fine tuning delay block has 5-bit resolution, giving 25 possible delays from which to choose for each full-scale setting (Register 0x36 and Register 0x3A = 00000b to 11000b).
The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.
The AD9510 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is −40°C to +85°C.
- Low jitter, low phase noise clock distribution
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, and mixed-signal front ends (MxFEs)
- High performance wireless transceivers
- High performance instrumentation
- Broadband infrastructure
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Product Selection Guide
RF Source Booklet
RF IC Product Overview
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008)
ADIsimCLK™ Reference Design Files
Once ADIsimCLK is installed, users may take advantage of saved design files with the extension, ".clk".
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Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Clock Requirements For Data Converters
(Electronic Design, 2/2005)
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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