12-Bit Mixed-Signal Front-End (MxFE® )Processor For Broadband Applications
The AD9863 utilizes two independent input clocks input for controlling all system clocks. The ADC sampling rate is controlled by the CLKIN1 input. The DAC sampling rate is controlled by the CLKIN2 input and a Phase-Lock-Loop clock multiplier.
A Flexible bi-directional 24-bit I/O bus is used to accommodate a variety of custom digital back ends or open market DSPs. In half duplex systems, the interface supports 24-bit parallel transfers or 12-bit interleaved transfers. In Full duplex systems, the interface supports an interleaved 12-bit ADC bus and an interleaved 12-bit Tx bus. The Flexible I/O bus reduces pin count and therefore required package size.
The AD9863 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC converter interpolation rate, control the ADC power down and TxDAC converter power down. The SPI allows for more programmable options for both the TxDAC path (for example, coarse and fine gain control, offset control for channel matching) and ADC path (for example, internal duty cycle stabilizer, 2's complement data format).
The AD9863 is packaged in a 64-pin lfCSP package (low profile, fine pitch chip scale package). The 64-pin lfCSP package footprint is only 9 mm by 9 mm and is less than 0.9 mm high fitting into tightly spaced applications such as PCMCIA cards.
- Broadband Access
- Broadband LAN
- Communications (Modems)
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For a list of compatible evaluation boards, please see the "DPG2" information on our Data Pattern Generator (DPG) High-Speed DAC Evaluation Platform page.