10-Bit Mixed-Signal Front-End (MxFE®)Processor
The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADCs and TxDAC Converters clock are generated within a timing generation block which utilizes user programmable options such as divide circuits, PLL multiplier and switches.
A Flexible bi-directional 20-bit I/O bus is used to accommodate a variety of custom digital back ends or open market DSPs. In half duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In Full duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit Tx bus. The flexible I/O bus reduces pin count and therefore required package size.
The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC converter interpolation rate, control the ADC power down and TxDAC power down. The SPI allows for more programmable options for both the TxDAC path (for example, coarse and fine gain control, offset control for channel matching) and ADC path (for example, internal duty cycle stabilizer, 2’s complement data format).
The AD9861 is packaged in a 64-pin lfCSP package (low profile, fine pitch chip scale package). The 64-pin lfCSP package footprint is only 9 mm by 9 mm and is less than 0.9 mm high fitting into tightly spaced applications such as PCMCIA cards.
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