The AD9985A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and horizontal sync (Hsync) and Coast signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.
The AD9985A’s on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained.
The AD9985 also offers full sync processing for composite sync and sync-on-green applications, variable analog input bandwidth control, variable SOGIN bandwidth control and selectable input filtering.
A clamp signal is generated internally or can be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985A is provided in a space-saving 80-lead LQFP surface-mount Pb-free plastic package, and is specified over the –40°C to +85°C temperature range.
- RGB graphics processing
- LCD monitors and projectors
- Plasma display panels
- Scan converters
- Digital TVs
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