The AD9983A includes a 140 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 1.8 V power supply and an analog input. Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
The AD9983A on-chip PLL generates a sample clock from the tri-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 140 MHz. With internal coast generation, the PLL maintains its output frequency in the absence of sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore the signal reference levels and to automatically calibrate out any offset differences between the three channels. The auto channel-to-channel gain matching feature can be enabled to minimize any gain mismatches between the three channels.
The AD9983A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9983A is provided in a space-saving 80-lead, Pb-free, LQFP surface-mount plastic package, and is specified over the 0°C to 70°C temperature range.Applications
- Advanced TVs
- Plasma display panels
- RGB graphics processing
- LCD monitors and projectors
- Scan converters
This designates products ADI does not recommend broadly for new designs.
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