12-Bit, 170/210 MSPS 3.3 V A/D Converter
The ADC requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V or 2.5 V CMOS logic.
Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A data sync input is supported for proper output data port alignment in CMOS mode and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (-40°C to +85°C).
- Wireless and Wired Broadband Communications
- Cable Reverse Path
- Communications Test Equipment
- Radar and Satellite Subsystems
- Power Amplifier Linearization
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs and DACs. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, frequency response plots, and more.
Staying Well Grounded
(Analog Dialogue, Vol. 46, June 2012)
Advanced Digital Post-Processing Techniques Enhance Performance in...
by Mark Looney, Analog Devices, Inc. (Analog Dialogue, Vol. 37, June 2003)
MS-2210: Designing Power Supplies for High Speed ADC
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
by Brad Brannon (Mobile Dev Design, 6/1/2003)
LVDS Ups A/D Converter Data Rates
... Over time, sample rates in analog-to-digital converters have increased steadily, thanks to some of the same...
DNL and Some of its Effects on Converter Performance
... by Brad Brannon, Analog Devices, Inc. (Wireless Design & Development, June 2001)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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