12-Bit, 20/40/65 MSPS, 3 V Analog-to-Digital Converter
The AD9235 is a family of monolithic, single 3 V supply, 12-bit, 20/40/65 MSPS analog-to-digital converters. This family features a high performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65 MSPS data rates and guarantee no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead thin shrink small outline package (TSSOP) and a 32-lead chip scale package (LFCSP) and is specified over the industrial temperature range (-40°C to +85°C).
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Recommended ADC Drivers
Recommended Clock Drivers
Recommended External Reference
- For improved thermal drift and gain accuracy , we recommend the ADR130 .
MS-2210: Designing Power Supplies for High Speed ADC
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by Rob Reeder, Analog Devices, Inc.
(Microwaves & RF, 7/2007)
Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
by Brad Brannon (Mobile Dev Design, 6/1/2003)
DNL and Some of its Effects on Converter Performance
... by Brad Brannon, Analog Devices, Inc. (Wireless Design & Development, June 2001)
Which ADC Architecture Is Right for Your Application?
Rarely Asked Questions
Too Hot or Too Cold May Be Just Right*
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