80 MHz Bandwidth, Dual IF Receiver
The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6673 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and up to 73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.
When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6673 can achieve up to 65.9 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6673 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.
By default the ADC output data is routed directly to the two external JESD204B serial output lanes. These outputs are at current mode logic (CML) voltage levels. Two modes are supported such that output coded data is either sent through one lane or two (L = 1; F = 4 or L = 2; F = 2). Single lane operation supports converter rates up to 125 MSPS. Synchronization input controls (SYNCINB± and SYSREF±) are provided.
- The configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane with up to two lanes.
- IF receiver includes two, 11-bit, 250 MSPS ADCs with programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate.
- Support for an optional RF clock input to ease system board design.
- Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
- An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices.
- Operation from a single 1.8 V power supply.
- Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.
- Diversity radio systems
- Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- I/Q demodulation systems
- Smart antenna systems
- Electronic test and measurement equipment
- RADAR receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The CVT-ADC-FMC-INTPZB interposer board allows certain Analog Devices' High-Speed ADC Evaluation Boards to be used on certain Xilinx® evaluation boards with a FMC connector. The adapter board uses the High Pin Count (HPC) version of the FMC connector, so it can be used on either LPC or HPC hosts (such as the KC705 or VC707). For a list of verified ADI ADC evaluation boards and Xilinx® evaluation boards, please see AD-ADC-FMC Adapter Board (Wiki page where we will have a table of high speed ADC eval boards and comments if needed).
JESD204 Serial Interface
The JESD204 and the JESD204B revision data converter serial interface standard was created through the JEDEC...
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