AD9433:  12-Bit 105/125 MSPS Analog-To-Digital IF Sampling Converter

The AD9433 is a 12-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is designed for ease of use. The product operates up to 125 Msps conversion rate ...More

To drive this ADC in DC-coupled applications, we suggest ADA4938-1. To drive this ADC in AC-coupled applications, we suggest AD8352.

AD9433:  12-Bit 105/125 MSPS Analog-To-Digital IF Sampling Converter

Product Description

The AD9433 is a 12-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is designed for ease of use. The product operates up to 125 Msps conversion rate and is optimized for outstanding dynamic performance in wideband and high IF carrier systems.

The ADC requires a +5V analog power supply and a differential encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3V or 2.5V logic.

A user-selectable, on-chip proprietary circuit optimizes spurious-free dynamic range (SFDR) versus signal-to-noise-and-distortion (SINAD) ratio performance for different input signal frequencies, providing as much as 83 dBc SFDR performance over the dc to 70 MHz band.

The encode clock supports either differential or single-ended input and is PECL-compatible. The output format is user-selectable for binary or two's complement and provides an overrange (OR) signal.

Fabricated on an advanced BiCMOS process, the AD9433 is available in a thermally enhanced 52-lead plastic quad flatpack specified over the industrial temperature range (-40°C to +85°C) and is pin-compatible with the AD9432.

Features

  • IF Sampling up to 350 MHz
  • SNR = 67.5 dB, Fin up to Nyquist at 105 MSPS
  • SFDR = 83 dBc, 70 MHz Fin at 105 MSPS
  • SFDR = 72 dBc, 150 MHz Fin at 105 MSPS
  • 2 Vp-p Analog Input Range Option
  • On-Chip Clock Duty Cycle Stabilization
  • On-Chip Reference and Track/Hold
  • SFDR Optimization Circuit
  • Excellent Linearity
    - DNL = ± 0.25 LSB (Typ)
    - INL = ± 0.5 LSB (Typ)
  • 750 MHz Full Power Analog Bandwidth
  • Power Dissipation = 1.35W at 125 MSPS
  • Two's Complement or Offset Binary Data Format

Diagrams

AD9433 Diagram
Functional Block Diagram for AD9433

Specifications

Resolution (Bits) 12bit
T-Put Rate 125000000SPS
# Chan 1
Supply V Multi(+3, +5)
Pwr Diss (max) 1.5W
Interface Par
Ain Range 2 V p-p
SNR (dB) 68dB
Pkg Type QFP

AD7352 - Differential Input, Dual, Simultaneous Sampling, 3 MSPS, 12-Bit, SAR ADC

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AD9230-11 - 11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter

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Part# Res Throughput Rate # of Inputs Operating Pwr Diss
AD9230-250 12 250MSPS 1 463mW
AD9626-170 12 170MSPS 1 291mW
AD9433-125 12 125MSPS 1 1.5W
AD9626-250 12 250MSPS 1 390mW
AD9230-170 12 170MSPS 1 407mW
AD9233-125 12 125MSPS 1 425mW
AD9430-170 12 170MSPS 1 1.43W