Documentation Errata for ADSP-TS201 TigerSHARC Processor Programming Reference (Revision 1.1, April 2005)


Chapter:  8 Page: 38
DOC ID: DOC-617
Change
Remove the following (it does not apply to the ADSP-TS201 processor):
In this next example with the same initial values, the result of the first slot is used in the second slot with unpredictable results.

R2 = R0 + R1 ; [Address] = R2 ;;
/* The results of using R2 as input for the memory store instruction here are unpredictable due to possible memory access stalls. The assembler flags this instruction as illegal. */

back to top

Chapter:  8 Page: 66
DOC ID: DOC-610
Change
In Table 8-1 (Resource Dependencies Stall List), the following stall conditions should be added:

Resource Dependencies Stall List (add to table 8-1)

Instruction 1

Instruction 2

Dependency

Stalls

Pipe Stage

Load Ureg from external or SOC instr.

Ureg1 = [external address];

Ureg1 = SOC_Ureg;

<...> = f (Ureg2)

or

Ureg2 = ...

or

... = Ureg2

If Ureg1 and Ureg2 are from the same register quad

External Access Delay

D

Load Ureg instr.

Ureg1 = [internal address];

<..> = f (Ureg2)

or

Ureg2 = ...

or

… = Ureg2

If Ureg1 and Ureg2 are from the same register quad and the internal memory access uses pre-modify

1

D

back to top

Chapter:  10 Page: 185
DOC ID: DOC-618
Change
Add the following text after the first paragraph under the heading "Function":
The description of the "Bit Clear/Set/Toggle" instruction is misleading for the case when a value in the input register "Rn" is used. The documentation states that the position of the bit that is being manipulated in the instruction is the 6-bit/5-bit value in register Rn for long/normal words, respectively. This implies that if there is a value in register Rn that is greater than 6/5 bits for long/normal words, that the value will be truncated to a 6/5 bit value. If Rn is greater than 6/5 bits, NO bits are manipulated (i.e. the result register "Rsd"/"Rs" for long/normal words is unchanged).

Also, add the following text (as an addendum) in the section titled "Example":
If the bit value in register Rn is greater than 6-bits (5-bits) for a long-word (normal-word) operation, the result in the destination register(s), Rsd (Rs), are unchanged. If an immediate value of greater than 6-bits (5-bits) is used, the immediate value gets truncated (via the opcode) to a 6-bit (5-bit) value, and therefore the appropriate bit is set/cleared/toggled via the instruction.

Example

r11:10 = btgl r7:6 by 0xf8;; // immediate value "0xf8" gets truncated to 6-bit value of "0x38"
If r7=0x00000000 and r6=0x00000000
then r11=0x01000000 and r10=0x00000000

r13:12 = btgl r7:6 by 0x38;; // immediate value "0x38" is a 6-bit value
If r7=0x00000000 and r6=0x00000000
then r11=0x01000000 and r10=0x00000000

r11:10 = btgl r7:6 by r4;; // value in register r4 exceeds 6-bits, therefore no updates to r11 or r10
If r7=0x00000000 and r6=0x00000000 and r4=0xfffffff8
then r11=0x00000000 and r10=0x00000000

r13:12 = btgl r7:6 by r1;; // value in register r1 is contained by 6-bits, therefore r13 or r12 are updated
If r7=0x00000000 and r6=0x00000000 and r1=0x00000038
then r11=0x01000000 and r10=0x00000000

back to top

Last Updated: September 13, 2005
Send Feedback X
content here.
content here.

Send Feedback

Close