Documentation Errata for ADSP-TS201 TigerSHARC Processor Programming Reference (Revision 1.1, April 2005)


Chapter:  8 Page: 38
DOC ID: DOC-617
Change
Remove the following (it does not apply to the ADSP-TS201 processor):
In this next example with the same initial values, the result of the first slot is used in the second slot with unpredictable results.

R2 = R0 + R1 ; [Address] = R2 ;;
/* The results of using R2 as input for the memory store instruction here are unpredictable due to possible memory access stalls. The assembler flags this instruction as illegal. */

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Chapter:  8 Page: 66
DOC ID: DOC-610
Change
In Table 8-1 (Resource Dependencies Stall List), the following stall conditions should be added:

Resource Dependencies Stall List (add to table 8-1)

Instruction 1

Instruction 2

Dependency

Stalls

Pipe Stage

Load Ureg from external or SOC instr.

Ureg1 = [external address];

Ureg1 = SOC_Ureg;

<...> = f (Ureg2)

or

Ureg2 = ...

or

... = Ureg2

If Ureg1 and Ureg2 are from the same register quad

External Access Delay

D

Load Ureg instr.

Ureg1 = [internal address];

<..> = f (Ureg2)

or

Ureg2 = ...

or

… = Ureg2

If Ureg1 and Ureg2 are from the same register quad and the internal memory access uses pre-modify

1

D

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Chapter:  9 Page: 19
DOC ID: DOC-1508
Change

The minimum refresh rate is incorrectly stated on this page. Change the text as follows (deletion and insertion):

The embedded DRAM system must refresh the data in every address at least once every 3.2 16 milliseconds to prevent data loss through process leakage; in other words, a refresh should occur once every 1.6 8 microseconds.

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Chapter:  9 Page: 54
DOC ID: DOC-1509
Change

The minimum refresh rate is incorrectly stated on this page. Change the text as follows (deletion and insertion):

CACMDB = CACMD_REFRESH | 750 3750;; 
/* set the refresh rate for embedded DRAM to every 750 3750 cycles */
CACMDB = 0x00000000;;
/* enable the cache associated with each memory block */
CACMDB = 0x1C3F8000;;
/* set cache/bus enable associated with each memory block */

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Chapter:  9 Page: 60
DOC ID: DOC-1510
Change

Need to update the programming values for refresh rates (to accomplish change of the minimum refresh rate from 3.2 milliseconds to 16 milliseconds). Change the text as follows (deletion and insertion):

  • 0x384 0x1194 for 900 4500 cycles (600 MHz CCLK)

  • 0x2EE 0xEA6 for 750 3750 cycles (500 – 599 MHz CCLK)

  • 0x258 0xBB8 for 600 3000 cycles (400 – 499 MHz CCLK)

  • 0x1C2 0x8CA for 450 2250 cycles, default value (300 – 399 MHz CCLK)

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Chapter:  9 Page: 61
DOC ID: DOC-1511
Change

Need to update the values in the programming example for refresh rates (to accomplish change of the minimum refresh rate from 3.2 milliseconds to 16 milliseconds). Change the text as follows (deletion and insertion):

J0 = (CACMD_REFRESH |0x1C2 0x8CA) ;;
CACMDB = J0 ;;
/* set the refresh rate to 450 2250 cycles for all blocks */
/* uses CACMD_REFRESH value from DEFTS201.H file */

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Chapter:  10 Page: 185
DOC ID: DOC-618
Change
Add the following text after the first paragraph under the heading "Function":
The description of the "Bit Clear/Set/Toggle" instruction is misleading for the case when a value in the input register "Rn" is used. The documentation states that the position of the bit that is being manipulated in the instruction is the 6-bit/5-bit value in register Rn for long/normal words, respectively. This implies that if there is a value in register Rn that is greater than 6/5 bits for long/normal words, that the value will be truncated to a 6/5 bit value. If Rn is greater than 6/5 bits, NO bits are manipulated (i.e. the result register "Rsd"/"Rs" for long/normal words is unchanged).

Also, add the following text (as an addendum) in the section titled "Example":
If the bit value in register Rn is greater than 6-bits (5-bits) for a long-word (normal-word) operation, the result in the destination register(s), Rsd (Rs), are unchanged. If an immediate value of greater than 6-bits (5-bits) is used, the immediate value gets truncated (via the opcode) to a 6-bit (5-bit) value, and therefore the appropriate bit is set/cleared/toggled via the instruction.

Example

r11:10 = btgl r7:6 by 0xf8;; // immediate value "0xf8" gets truncated to 6-bit value of "0x38"
If r7=0x00000000 and r6=0x00000000
then r11=0x01000000 and r10=0x00000000

r13:12 = btgl r7:6 by 0x38;; // immediate value "0x38" is a 6-bit value
If r7=0x00000000 and r6=0x00000000
then r11=0x01000000 and r10=0x00000000

r11:10 = btgl r7:6 by r4;; // value in register r4 exceeds 6-bits, therefore no updates to r11 or r10
If r7=0x00000000 and r6=0x00000000 and r4=0xfffffff8
then r11=0x00000000 and r10=0x00000000

r13:12 = btgl r7:6 by r1;; // value in register r1 is contained by 6-bits, therefore r13 or r12 are updated
If r7=0x00000000 and r6=0x00000000 and r1=0x00000038
then r11=0x01000000 and r10=0x00000000

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Chapter:  14 Page: 11
DOC ID: DOC-1512
Change

Change the glossary entry for refresh rate (to accomplish change of the minimum refresh rate from 3.2 milliseconds to 16 milliseconds). Change the text as follows (deletion and insertion):

Refresh Embedded DRAM Memory

The embedded DRAM system must refresh the data in every address at least once every 3.2 16 milliseconds to prevent data loss through process leakage.

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Last Updated: March 04, 2014
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