|Chapter: 1||Page: 22|
|DOC ID: DOC-559|
|In the bottom paragraph, delete:
see "Bus Arbitration Protocol" on page 8-38
This cross reference is not relevant to the discussion in the paragraph.
|Chapter: 1||Page: 31|
|DOC ID: DOC-560|
|In the sixth paragraph, the following line:
Host Bus Grant (HBG) is returned by the TigerSHARC processors when the current master grants bus by asserting HBR.Should change to:
Host Bus Grant (HBG) is returned by the current TigerSHARC master upon completion of its external access, when an external master has asserted HBR.
|Chapter: 2||Page: 32|
|DOC ID: DOC-592|
|The description of the sequencer status (SQSTAT) register is incorrect. The following bit descriptions in SQSTAT need to change:|
Remove all references to the non-existent BTBMOD bit field.
|Chapter: 2||Page: 76|
|DOC ID: DOC-602|
|The documentation incorrectly states that:
In USER mode with the SYS_REG_WE strap pin disabled at reset, the SDRCON register can be written only once after hardware reset and cannot be changed during system operation - subsequent writes to SDRCON are ignored.
Replace the above text with the following:
In SUPERVISOR mode, SDRCON is write once after reset if the SYS_REG_WE strap pin is disabled. If the SYS_REG_WE strap pin is enabled, there are no write restrictions for SDRCON in SUPERVISOR mode. SDRCON can never be written in USER mode regardless of the SYS_REG_WE strap pin setting.
|Chapter: 2||Page: 80|
|DOC ID: DOC-661|
|The text at the top of this page refers to the incorrect clock. Change from: |
The BMAX register is set with the maximum number of internal clock cycles (CCLK) for which ...
The BMAX register is set with the maximum number of SOCCLK cycles for which ...
|Chapter: 2||Page: 83|
|DOC ID: DOC-622|
|In the description paragraph for the IDCODE register, change the reference to the EMUCTL register (in the second sentence) to IDCODE.|
In Figure 2-45 (IDCODE Register Bit Descriptions), change ID31-28 to IDCODE31-28, and change ID27-0 to IDCODE27-0.
In footnote 1 of Figure 2-45 (IDCODE Register Bit Descriptions), change ID27-0 to IDCODE27-0.
|Chapter: 2||Page: 92|
|DOC ID: DOC-633|
|Add the following paragraph to the Cycle Counter (CCNTx) Registers section:
To keep both of the cycle counter registers coherent between the two write accesses, a shadow register is used to temporarily hold the value written for the CCNT0 register. This temporary value is not written into the actual CCNT0 register until a write has also been issued to the CCNT1 register. So, the CCNT0 and CCNT1 registers must also be written to in the same order as they are read; write to CCNT0 first, then write to CCNT1 to allow for coherent writes of these registers.
|Chapter: 4||Page: 3|
|DOC ID: DOC-597|
|The last two lines of the third paragraph incorrectly state:
If the timer is active (TMRxRN bit is set), writing a value to the TMRINxH/L register has no effect. Writing a different value to TMRINxH/L while the timer is operating changes the initial value after the next expiration of the timer (when TMRINxH/L value is copied again to the timer).
This statement is not accurate. What actually happens is that a new value written into TMRINxH/L register immediately takes effect, even when the timer is already running. Change these sentences to:
If the timer is active (TMRxRN bit is set), writing a value to the TMRINxH/L register has an immediate effect. Writing a different value to TMRINxH/L while the timer is operating changes current timer operation, and the value is used as the initial value after the next expiration of the timer (when TMRINxH/L value is copied again to the timer).
|Chapter: 6||Page: 21|
|DOC ID: DOC-600|
|Use the following two sections to replace the "Vector Interrupt" section. Also, add a cross reference from the KERNEL entry in Table 6-1 (page 6-19) to the new "Kernel Interrupt section.|
|Chapter: 7||Page: 37|
|DOC ID: DOC-603|
|In Table 7-5 (DMA Channel Priority), the AutoDMA Register names are missing from the Channel column. These table cells should be shown as follows:|
Channel 13 (AUTODMA1)
Channel 12 (AUTODMA0)
|Chapter: 7||Page: 43|
|DOC ID: DOC-616|
|In the Blocks and Chain Loading section, add clarification as follows:
The DMA channel is disabled between DMA sequences in a chain (during chaining).
|Chapter: 8||Page: 13|
|DOC ID: DOC-601|
|The documentation erroneously states that:
In USER mode, SYSCON is write once after reset, unless the SYS_REG_WE strap pin is enabled. In Supervisor mode, SYSCON has no write restrictions.
Remove erroneous text and replace with:
In SUPERVISOR mode, SYSCON is write once after reset if the SYS_REG_WE strap pin is disabled. If the SYS_REG_WE strap pin is enabled, there are no write restrictions for SYSCON in SUPERVISOR mode. SYSCON can never be written in USER mode regardless of the SYS_REG_WE strap pin setting.
The text on page 2-73 must also be updated to match this change.
|Chapter: 8||Page: 50|
|DOC ID: DOC-606|
|In paragraph 2, that last two sentences incorrectly state the SDRAM sizes per bank and the total amount of SDRAM supported by the TS201. The following two sentences should be changed from:
The SDRAM interface provides a glueless interface with standard SDRAMs—6M bits, 64M bits, 128M bits, 256M bits, and 512M bits. The TigerSHARC processor directly supports a maximum of 64M words x 32 bits of SDRAM per bank for a total of 856M words.
The SDRAM interface provides a glueless interface with standard SDRAMs — 16Mbits, 64Mbits, 128Mbits, 256Mbits, and 512Mbits. The TigerSHARC processor directly supports a maximum of 64M words x 32 bits of SDRAM per bank for a total of 256M words.
|Chapter: 8||Page: 78|
|DOC ID: DOC-639|
In table 8-13 (Data Throughput Rates), the formulas in the last two rows need to be updated. Change from:
|Chapter: 9||Page: 9|
|DOC ID: DOC-593|
|In the first paragraph, the description of link block completion is not accurate. The text should change from:|
When LxBCMPI is sampled active, the receiving link port transfers this information to the DMA together with its DMA request. The TCB word counters are cleared by the DMA and the DMA sequence completes.The text should change to:
When LxBCMPI is sampled active, the receiving link port transfers this information to the DMA together with its DMA request. The TCB word counters retain the final number until the next initialization, and the DMA sequence completes.
|Chapter: 9||Page: 24|
|DOC ID: DOC-591|
|In Figure 9-16 and Table 9-5, the LTCTLx register's bit 0 is identified as "LTEN".|
Change the identifier for this bit to "TEN". (This change makes Figure 9-16 and Table 9-5 agree with Figure 2-32 and the defts20x.h files.)
|Chapter: 11||Page: 29|
|DOC ID: DOC-634|
|Please delete the reference to the "ADSP-TS201S MP System Simulation and Analysis Cluster Bus Topology -- Signal Integrity and PCB Design Considerations" technical article.|
This article is not available.
|Chapter: n/a||Page: 8|
|DOC ID: DOC-558|
|In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.|
In the Preface, the IP address of the FTP server is no longer valid. Use ftp://184.108.40.206 instead.