SHARC PROCESSOR ARCHITECTURAL OVERVIEW Super Harvard Architecture

Analog Devices' 32-Bit Floating-Point SHARC® Processors are based on a Super Harvard architecture that balances exceptional core and memory performance with outstanding I/O throughput capabilities. This "Super" Harvard architecture extends the original concepts of separate program and data memory busses by adding an I/O processor with its associated dedicated busses. In addition to satisfying the demands of the most computationally intensive, real-time signal-processing applications, SHARC processors integrate large memory arrays and application-specific peripherals designed to simplify product development and reduce time to market.

The SHARC processor portfolio currently consists of four generations of products providing code-compatible solutions ranging from entry-level products priced at less than $10 to the highest performance products offering fixed- and floating-point computational power to 450 MHz/2700 MFLOPs. Irrespective of the specific product choice, all SHARC processors provide a common set of features and functionality useable across many signal processing markets and applications. This baseline functionality enables the SHARC user to leverage legacy code and design experience while transitioning to higher-performance, more highly integrated SHARC products.

Common Architectural Features

  • 32/40-Bit IEEE Floating-Point Math
  • 32-Bit Fixed-Point Multipliers with 64-Bit Product & 80-Bit Accumulation
  • No Arithmetic Pipeline; All Computations Are Single-Cycle
  • Circular Buffer Addressing Supported in Hardware
  • 32 Address Pointers Support 32 Circular Buffers
  • Six Nested Levels of Zero-Overhead Looping in Hardware
  • Rich, Algebraic Assembly Language Syntax
  • Instruction Set Supports Conditional Arithmetic, Bit Manipulation, Divide & Square Root, Bit Field Deposit and Extract
  • DMA Allows Zero-Overhead Background Transfers at Full Clock Rate Without Processor Intervention

First Generation SHARC products offer performance to 66 MHz/ 198 MFLOPs and form the cornerstone of the SHARC processor family. Their easy-to-use Instruction Set Architecture that supports both 32-bit fixed-point and 32/40-bit floating data formats combined with large memory arrays and sophisticated communications ports make them suitable for a wide array of parallel processing applications including consumer audio, medical imaging, military, industrial, and instrumentation.

Second Generation SHARC products double the level of signal processing performance (100MHz / 600MFLOPs) offered by utilizing a Single-Instruction, Multiple-Data (SIMD) architecture. This hardware extension to first generation SHARC processors doubles the number of computational resources available to the system programmer. Second generation products contain dual multipliers, ALUs, shifters, and data register files - significantly increasing overall system performance in a variety of applications. This capability is especially relevant in consumer, automotive, and professional audio where the algorithms related to stereo channel processing can effectively utilize the SIMD architecture.

Third Generation SHARC products employ an enhanced SIMD architecture that extends CPU performance to 450 MHz/2700 MFLOPs. These products also integrate a variety of ROM memory configurations and audio-centric peripherals design to decrease time to market and reduce the overall bill of materials costs. This increased level of performance and peripheral integration allow third generation SHARC processors to be considered as single-chip solutions for a variety of audio markets.

The fourth generation of SHARC® Processors, now includes the ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications

Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

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