The ADSP-21160 is the first processor in Analog Devices' second generation of SHARC DSPs. The new ADSP-21100 family is designed to deliver the highest frequency core and computational bandwidth possible while maintaining source code compatibility with the first generation. This second generation provides major performance increases through an increase in core frequency and architectural enhancements. Table 1 identifies major changes.

The core clock frequency of the initial ADSP-21160 is 100MHz, two and a half times that of the ADSP-21060. Significant performance increases can be obtained by simply porting existing ADSP-21060 code to the ADSP-21160.

The ADSP-21160 was designed to be assembly source code compatible with the first generation. It takes advantage of this core frequency increase, requiring minor code modification. Due to changes in the memory mapped addresses of a relatively small number of control and status registers, as well as minor changes to bit positions within these registers, the use of a symbol definition file will facilitate code porting. The attached symbol definition file supports the ADSP-21160. Code porting will require changing the source code to include this file. This application note outlines the details of porting ADSP-2106x code to the ADSP-21160.

Table 1. Differences between the ADSP-21160 DSP and ADSP-2106x DSPs
Feature ADSP-21160 Differences Feature Affected
ASTAT / FLAGs FLAG values moved from the ASTAT register to the new FLAGS register. ASTAT, FLAG3-0.
Interrupts Four new interrupts for new DMA channels. Link port interrupt latching and masking moved to new register LIRPTL. Link port summation interrupt mask added to IMASK. Interrupt Vector Table, IRPTL, IMASK, IMASKP.
Status Stack Increased from 5 levels to 15 levels deep. ASTAT, MODE1.
Memory Long Word (64-bit) Address Space added. Internal Address space increased from 4Mb to 8Mb. Normal Word, Short shift, MMS, and External Memory Spaces shift. Internal memory organization significantly modified. Architecture File / Linker Description File.
PX Register PX Register expanded from 48-bits to 64-bits (PX1 from 16 to 32-bits) to accommodate 64-bit buses. PX1
DAG2 Registers expanded from 24-bits to 32-bits. B15-8, I15-8, L15-8, M15-8.
Circular Buffering (DAG1, DAG2) Global Circular Buffer Enable Control bit (CBUFEN) added to MODE1 register. All DAG Register Sets (B15-0, I15-0, L15-0, M15-0), MODE1.
DMA Four new dedicated link port channels added. DMA parameter (IIx, IMx, Cx, etc.) assignments shifted. DMASTAT register expanded for new channel. Packing modes (PMODE) expanded in DMACx. All DMA parameters (IIx, IMx, Cx, etc.), DMASTAT, DMACx.
Link Ports Data path width (LxDAT) expanded from 4-bits to 8-bits. New control bit to configure for 4 or 8-bit transfers added to LCTL. Two new control bits (LxLCKD1-0) replace LCLKx2X in LCOM. LCTL expanded to LCTL1-0. Control bits regrouped in both LCTL and LCOM. LCTL, LCOM
External Port External Port data width expanded from 48-bits to 64-bits. HPM field in SYSCON expanded to support new packing modes. WAIT modes significantly modified. SYSCON, WAIT.

Further improvements in performance can be realized by optimizing the ported code for the architectural enhancements of the ADSP-21160. These architectural improvements include the addition of a second set of computation units with a register file and an increase in the data bus widths to 64-bits. These enhancements represent a SIMD (Single Instruction Multiple Data) execution model. This application note does not discuss techniques to optimize for SIMD architecture.

This application note consists of three parts. First, it discusses the differences between the two core architectures that must be addressed for porting code. Second, there is a discussion of the differences in the peripherals between the ADSP-21060 and the ADSP-21160 to facilitate porting code, which uses these features. Third, this note discusses how to use VisualDSP 4.0 to develop code for the ADSP-21160. This application note assumes that the reader is familiar with the first generation SHARC family.

Core Architecture

For the most part, all algorithm source code is completely compatible with the ADSP-21160 and requires minor, if any, modification. Most code porting issues are related to core control register initialization and I/O processor control register programming. If the ported code uses symbolic references for control bit settings, the core initialization will also require very minor modification. A symbol definition file for the ADSP-21160 (def21160.h) is included at the end of this application note. It is intended to be closely compatible with the def21060.h file for the ADSP-2106x. Code porting may only require changing to the new symbol definition file. Several IOP control registers have changed and require minor modification of control words used to program them. This application note details those control registers that have been changed.

In general, all instructions that write explicit data words to the control registers of the ADSP-21060 should use either the symbol definitions of the def21160.h file or should be closely examined to ensure they are compatible with the control register set of the ADSP-21160. For example, four of the upper control bits of the MODE1 register, which were reserved bits on the ADSP-21060, are now used to configure specific modes of operation on the ADSP-21160. If a control word that inadvertently sets or clears these bits is written to the MODE1 register, it may cause undesired results.

Computation Units

The changes for the computation units that affect ADSP-21060 code are the addition of a second set of computation units and a new status/control register for the FLAGs. These modifications cause minor changes to the status registers associated with the computation units.


Due to the addition of a second set of computational units, the ADSP-21160 includes a second arithmetic status register. Adding these resulted in a change to the name of the original arithmetic status register (ASTAT). There are now two arithmetic status registers (ASTATx and ASTATy). Since ADSP-21060 code will not make use of this second set of computation units, only ASTATx will be used. This usage pattern is due to the fact that ASTATx is associated with the primary set of computation units on the ADSP-21160 and is active by default. In order to be code compatible with the ADSP-2106x, the assembler for the ADSP-21160 accepts both ASTAT and ASTATx for the ASTATx register. So, instructions that directly write to ASTAT or perform bit manipulation operations on ASTAT will require no modification. The same applies to the STKY register.


The flag values have moved from the ASTAT register and now reside in a new register named FLAGS. This change removes any confusion for testing and modification of the FLAGs due to pushing and popping of the status stack. This register will contain the values of FLAG3:0. So, all instructions that modify or test the values of these FLAGs will have to be changed to affect the FLAGS register instead of the ASTAT register.

Program Sequencer

The program sequencer of the ADSP-21160 differs from the ADSP-21060 as far as interrupts and context switching are concerned. The ADSP-21160 has four new dedicated DMA channels, and these channels have four new dedicated interrupts. This difference causes a change in the interrupt vector table and the IRPTL/IMASK registers. Additionally, a new interrupt, the Illegal Input Condition Detected Interrupt (IICDI), has been added to facilitate code optimization for the ADSP-21160. The status stack of the ADSP-21160 is larger in size to allow an increase in interrupt nesting and context switching.


Due to the increase in DMA channels from 10 on the ADSP-21060 to 14 on the ADSP-21160, four additional interrupts have been added. The interrupt vector locations for these interrupts were added in the middle of the interrupt vector table, shifting the vector addresses of many interrupts. Modify your source code for the interrupt vector table and architecture file memory allocation for this table to accommodate this change. The interrupt vectors and vector addresses remain the same for all interrupts up to and including the SPORT1 transmit interrupt. The only exception is that the SPORT0 and SPORT1 transmit interrupts are not shared with the link ports. The link ports each have dedicated DMA channels, rather than sharing two each with the serial ports and the external port. The dedicated link port interrupt vector addresses begin at 0x38 and run to 0x4f. This change to the table results in a 16 address location shift in the vector addresses of all the interrupts that follow. The new interrupt vector table appears in Table 2 in order from highest to lowest priority.

Table 2. ADSP-21160 Interrupt Vector Table
Vector Address IRQ Name Function
IRPTL 0 0x00 EMUI Emulator (read-only, non-maskable)
IRPTL 1 0x04 RSTI Reset (read-only, non-maskable)
IRPTL 2 0x08 IICDI Illegal Input Condition Detected
IRPTL 3 0x0C SOVFI Status, loop, or mode stack overflow; or PC stack full
IRPTL 4 0x10 TMZHI Timer=0 (high priority option)
IRPTL 5 0x14 VIRPTI Vector Interrupt
IRPTL 6 0x18 IRQ2I asserted
IRPTL 7 0x1C IRQ1I asserted
IRPTL 8 0x20 IRQ0I asserted
IRPTL 9 0x24 - reserved
IRPTL 10 0x28 SPR0I DMA Channel 0 - SPORT0 Receive
IRPTL 11 0x2C SPR1I DMA Channel 1 - SPORT1 Receive
IRPTL 12 0x30 SPT0I DMA Channel 2 - SPORT0 Transmit
IRPTL 13 0x34 SPT1I DMA Channel 3 - SPORT1 Transmit
LIRPTL 0 0x38 LP0I DMA Channel 4 - Link Buffer 0
LIRPTL 1 0x3C LP1I DMA Channel 5 - Link Buffer 1
LIRPTL 2 0x40 LP2I DMA Channel 6 - Link Buffer 2
LIRPTL 3 0x44 LP3I DMA Channel 7 - Link Buffer 3
LIRPTL 4 0x48 LP4I DMA Channel 8 - Link Buffer 4
LIRPTL 5 0x4C LP5I DMA Channel 9 - Link Buffer 5
IRPTL 15 0x50 EP0I DMA Channel 10 - Ext. Port Buffer 0
IRPTL 16 0x54 EP1I DMA Channel 11 - Ext. Port Buffer 1
IRPTL 17 0x58 EP2I DMA Channel 12 - Ext. Port Buffer 2
IRPTL 18 0x5C EP3I DMA Channel 13 - Ext. Port Buffer 3
IRPTL 19 0x60 LSRQI Link Port Service Request
IRPTL 20 0x64 CB7I Circular Buffer 7 Overflow
IRPTL 21 0x68 CB15I Circular Buffer 15 Overflow
IRPTL 22 0x6C TMZLI Timer=0 (low priority option)
IRPTL 23 0x60 FIXI Fixed-point overflow
IRPTL 24 0x74 FLTOI Floating-point overflow exception
IRPTL 25 0x78 FLTUI Floating-point underflow exception
IRPTL 26 0x7C FLTII Floating-point invalid exception
IRPTL 27 0x80 SFT0I User software interrupt 0
IRPTL 28 0x84 SFT1I User software interrupt 1
IRPTL 29 0x88 SFT2I User software interrupt 2
IRPTL 30 0x8C SFT3I User software interrupt 3
IRPTL 31 0x90 - reserved

This change to the interrupt vector table means that you must include an additional 16 instructions or instruction place holders for the four new dedicated link port interrupts (eight instructions between SPTI1 and LP2I and eight between LP3I and EP0I). Also, move any LPORT interrupt service routines from the shared channel vector addresses to the new dedicated link port interrupt vector addresses. Further, you must modify the memory allocation for the interrupt vector table in the architecture file to be at least 148 address locations in length (e.g. 0x40000 to 0x40093).

Interrupt forcing/clearing and masking differs also, but only slightly and only as far as the link port interrupts are concerned. Setting and clearing bits in the IRPTL and IMASK registers remains the same for all interrupts that are not associated with the link ports. Individual link port interrupt forcing and masking is now controlled in a new register called LIRPTL (Link Port Interrupt Latch). Also, a second level of interrupt masking control for all link port interrupts has been added, which controls the enabling of all link port interrupts. This control bit is called the LPSUMI bit in the IMASK register. To enable an interrupt for a particular link port, you must unmask the assigned link buffer interrupt in LIRPTL and the LPSUMI bit in the IMASK register.

A symbol definition file (def21160.h) and a runtime header file (ivt.asm) for the interrupt vector table appear at the end of this application note. These files can be used to facilitate the porting of code and as a quick reference.

Interrupt Nesting

The interrupt mask pointer bits for the link port interrupts on the ADSP-21160 are in bit positions 29-24 of the LIRPTL control register. These bits are used during interrupt nesting. If you are not reading or writing the IMASKP register, you should not be concerned with this change.

Status Stack

The status stack on the ADSP-21160 differs from the ADSP-21060, changing from five levels deep to 15 levels deep, which facilitates the handling of deeper interrupt nesting and context switching. If you were running into problems with overflowing the status stack, the ADSP-21160 lets you avoid having to manually save and restore ASTAT and MODE1 on a context switch or interrupt service. This feature allows you to push and pop the status stack to 15 levels.


The memory map for the ADSP-21100 architecture has been modified to support up to 8 MBits of on-chip SRAM. Also, a new internal address space has been added to facilitate 64-bit internal memory accesses (long word addressing). Long word addressing allows you to access two 32-bit data words in one cycle over any of the three data buses (PM, DM, or IO). These changes have caused a shift in the normal word, short word, MMS, and external memory addressing. Modify your architecture file (Linker Description File for VisualDSP) to accommodate this change to the memory map. For all changes to the architecture file (or LDF file), refer to the ADSP-21160 Memory Map (Figure 7-4) and the ADSP-21160 Internal Memory Space (Figure 7-6) in the ADSP-21160 SHARC specification. The internal memory organization and PX register have changed as well. The differences are outlined in the following sections.

Normal Word Address Space

Normal word addressing on the ADSP-21160 begins at address 0x40000 and ends at 0x7FFFF. This range is twice the internal address space for the ADSP-2106x. For the ADSP-21160, there are 4Mbits of internal SRAM, which is divided into Block 0 (0x40000 to 0x4FFFF) and Block 1 (0x50000 to 0x5FFFF). This leaves addresses in the range 0x60000 to 0x6FFFF as reserved space, which should not be accessed. Reads from this space return zeroes, and writes fall into the bit bucket.

Short Word Addressing Space

Short word addressing on the ADSP-21160 begins at address 0x80000 and ends at 0xBFFFF. Block 0 runs from 0x80000 to 0x9FFFF. Block 1 runs from 0xA0000 to 0xBFFFF. This leaves addresses in the range 0xC0000 to 0xFFFFF as reserved space, which should not be accessed. Reads from this space return zeroes, and writes fall into the bit bucket. Figure 1 shows the internal addressing space of the ADSP-21160.

Multi-processor Memory Address Space

Multi-processor memory space begins at address 0x100000 and ends at address 0x7FFFFF. Because the internal addressable space of the ADSP-21160 is twice that of the ADSP-21060, the spacing of each ID in MMS space differs. To accommodate this increase in on-chip addressing, the offset of each individual ID's address space has increased from 0x80000 on the ADSP-21060 to 0x100000 for the ADSP-21160. Refer to Figure 2 for detail.

The short-word and long-word address space of each individual ID are not accessible through MMS space. Modify code that accesses short-word space through MMS to access normal word space.


Figure 1. ADSP-21160 Internal Memory Map

External Memory Address Space

External memory address space on the ADSP-21160 begins at address 0x800000 and ends at address 0xFFFFFFFF. This difference is a decrease of about 8 Mwords of external addressable space compared to the ADSP-21060 and is due to the increase in internal and MMS space addressing. This decrease is insignificant when compared to the total 4Gwords of addressable space.

Note that an example linker description file (21160.ldf) appears at the end of this application note for reference. The memory{} command in the LDF file describes the ADSP-21160's memory space.

Use Figure 2 as a reference for MMS and external memory addressing of the ADSP-21160.


Figure 2. ADSP-21160 Internal & External Memory Map

Internal Memory Organization

The ADSP-21160 internal memory organization differs from that of the ADSP-21060. The internal SRAM is divided into two blocks, which are sub-divided into four columns. Each column is 16-bits wide and 32k deep. This modification allows 48-bit instructions to be packed more efficiently and provides greater instruction memory capacity for the same physical memory size. Be aware that this change will effect the address assignments for mixing of 48-bit (or 40-bit) and 32-bit words. The most efficient starting address for 32-bit words is determined using a formula, which is outlined in the Memory chapter of the ADSP-21160 SHARC specification. Refer to this chapter for more details on the internal memory organization and most efficient address calculation for mixing of 48-bit (or 40-bit) and 32-bit words.

PX Register

The PX register is expanded to 64-bits to accommodate the modification to the internal pm and dm data bus width (expanded to 64-bits). The PX1 register is expanded to 32 bits due to this change, and this may impact instructions that use this sub-register.

Refer to the data bus alignment for PX register transfers, which are outlined in the memory section of the ADSP-21160 SHARC specification for more detail.

Data Address Generators

The ADSP-21160's DAGs (Data Address Generators) differ slightly from the ADSP-2106x's . DAG2's addressable space has been extended, and a global circular buffer enable has been added that controls both DAGs.


All of the registers of DAG2 have been extended to 32-bits (24-bits on ADSP-21060) and are capable of accessing the entire memory space of the ADSP-21160. Note that even though the DAG2 register file has been extended to 32-bits in width, the instruction fetch hardware is only 24-bits in width. For example, only 24-bits of the DAG2 I and M registers are used in computing program counter values. (example: jump (i8,m8);)

Circular Buffers

The only difference in circular buffer support is a global circular buffer enable (CBUFEN), which effects all of the DAG register sets and is located in the MODE1 register. This control bit disables circular buffering on context switches and eliminates the need to save and restore the B and L values when using the DAG pointers during a context switch. Circular buffering will be enabled for a DAG register set if the L register contains a non-zero value and the CBUFEN bit is set in the MODE1 register. Be sure to set the CBUFEN bit in the MODE1 register if using circular buffering.

Peripherals (IO Processor)

The ADSP-21160 adds four new DMA channels for a total of 14 channels. The ADSP-21160 DMA controller has dedicated DMA channels for the six link port buffers, which causes a change in the DMA parameter assignments as well as the external port DMA control registers.


There are no changes to the SPORT DMA features. All code that uses these features will be completely compatible.


There have been several changes to the LCTL and LCOM registers that will effect the control word settings of these registers for DMA configuration. See the Link Port section of this application note for details.

Due to the additional dedicated DMA channels for the link port buffers, the ADSP-21160 DMA parameter register assignments for each link buffer differ from the assignments of the ADSP-21060. The ADSP-21160 link buffer DMA parameters have the assignments that are outlined in Table 3.

Table 3. Link Buffer DMA Channel Assignment
Register Name(s) Description
II4, IM4, C4, CP4, GP4, DB4, DA4 DMA Channel 4 Parameter Registers (Link Buffer 0)
II5, IM5, C5, CP5, GP5, DB5, DA5 DMA Channel 5 Parameter Registers (Link Buffer 1)
II6, IM6, C6, CP6, GP6, DB6, DA6 DMA Channel 6 Parameter Registers (Link Buffer 2)
II7, IM7, C7, CP7, GP7, DB7, DA7 DMA Channel 7 Parameter Registers (Link Buffer 3)
II8, IM8, C8, CP8, GP8, DB8, DA8 DMA Channel 8 Parameter Registers (Link Buffer 4)
II9, IM9, C9, CP9, GP9, DB9, DA9 DMA Channel 9 Parameter Registers (Link Buffer 5)
External Port DMA

Due to the 64-bit external port of the ADSP-21160, additional packing modes are now supported. This difference causes minor changes to the bit positions of the DMACx control registers. The PMODE field is expanded from two to three bits to select additional packing modes, and a control bit PRIO has been added. Modifications must be made to any control words that configure these registers. The symbol definition file (def21160.h) that appears at the end of this application note can be used to facilitate these changes.

The external port section of this application note contains more details on packing modes and other modifications to the external port. For a more detailed description of the external bus alignment and packing modes of the external port, refer to the DMA and External Memory chapters of the ADSP-21160 SHARC specification.

Due to the additional dedicated DMA channels for the link port buffers, the ADSP-21160 DMA parameter register assignments for each external port buffer differ from the assignments of the ADSP-21060. The ADSP-21160 external port buffer DMA parameters have the assignments that are outlined in Table 4.

Table 4. External Port Buffer DMA Channel Assignment
Register Name(s) Description
II10, IM10, C10, CP10, GP10, DB10, DA10 DMA Channel 10 Parameter Registers (Ext. Port Buffer 0)
II11, IM11, C11, CP11, GP11, DB11, DA11 DMA Channel 11 Parameter Registers (Ext. Port Buffer 1)
II12, IM12, C12, CP12, GP12, DB12, DA12 DMA Channel 12 Parameter Registers (Ext. Port Buffer 2)
II13, IM13, C13, CP13, GP13, DB13, DA13 DMA Channel 13 Parameter Registers (Ext. Port Buffer 3)

The ADSP-21160 DMASTAT register has changed to accommodate the four new DMA channels. Instructions that directly read or test the bits of this register should be modified accordingly.

Link Port

The ADSP-21160 link port control registers have been modified to some extent. The link port data lines have expanded from four bits to eight bits but can be configured to operate with either four or eight bit transfers. This difference forces the addition of a new control bit in the link port control registers. Also, the control bits for the link ports have been reorganized and are now grouped differently in the control registers. Pay close attention to these changes and modify the control words used to program these registers accordingly.

LCTL Register

The ADSP-21160 link buffer control register (LCTL) incorporates an additional control bit (LxDPWID), which controls the data path width (four or eight bits) for the each link port, (default configuration is four bit data path width). Also, several bits from the link common control register (LCOM) have been regrouped and are now included in the LCTL register. These bits include LxEXT, which controls the data word width (32 or 48 bits) and LxLCKD0 and LxLCKD1, which replace LCLKX2x and control the transfer data rates (now 0.25x, 0.33x, 0.5x, and 1x the core clock rate). The LCTL register also includes L2DDMA and LPDRD, whose functionality has not changed. In order to accommodate this expansion, LCTL was extended to 64 bits and has become two registers: LCTL0 and LCTL1. The bit positions and descriptions of the LCTL0 and LCTL1 control registers are outlined in Table 5.

Table 5. LCTL1:0 Control Registers
Register Bit # Name Description
LCTL0 0 + 10x LxEN LBUFx enable
LCTL0 1 + 10x LxDEN LBUFx DMA enable
LCTL0 2 + 10x LxCHEN LBUFx chaining enable
LCTL0 3 + 10x LxTRAN LBUFx direction: 1=transmit, 0=receive
LCTL0 4 + 10x LxEXT LBUFx extended word size: 1=48-bit, 0=32-bit
LCTL0 5 + 10x LxCLKD0 LBUFx clock ratio select bit0
LCTL0 6 + 10x LxCLKD1 LBUFx clock ratio select bit1
LCTL0 7 + 10x Lx2DDMA LBUFx enable 2-dimensional DMA
LCTL0 8 + 10x LxPDRD LBUFx disable internal pulldown resistor for LxCLK and LxACK
LCTL0 9 + 10x LxDPWID LBUFx data path width: 1=8-bit, 0=4-bit
LCTL0 30-31   reserved
LCTL1 0 + 10y LyEN LBUFy enable
LCTL1 1 + 10y LyDEN LBUFy DMA enable
LCTL1 2 + 10y LyCHEN LBUFy chaining enable
LCTL1 3 + 10y LyTRAN LBUFy direction: 1=transmit, 0=receive
LCTL1 4 + 10y LyEXT LBUFy extended word size: 1=48-bit, 0=32-bit
LCTL1 5 + 10y LyCLKD0 LBUFy clock ratio select bit0
LCTL1 6 + 10y LyCLKD1 LBUFy clock ratio select bit1
LCTL1 7 + 10y Ly2DDMA LBUFy enable 2-dimensional DMA
LCTL1 8 + 10y LyPDRD LBUFy disable internal pulldown resistor for LyCLK and LyACK
LCTL1 9 + 10y LyDPWID LBUFy data path width: 1=8-bit, 0=4-bit
LCTL1 30-31   reserved

The LxCLKD1 and LxCLKD0 bits of LCTL control the core clock division for the transfer rate on each individual LBUFx. Table 6 details the possible settings.

Table 6. Link Clock Configuration
LxCLKD1 LxCLKD0 Core Clock : LCLK
0 0 4:1 (Initial Value)
0 1 1:1
1 0 2:1
1 1 3:1
LCOM Register

Due to the regrouping of some of the control bits, the ADSP-21160 link port common control register (LCOM) has changed. Modify control words used to program this register accordingly. The bit positions and descriptions of the LCOM control register are outlined in Table 7.

Table 7. LCOM Control Register
Register Bit # Name Description
LCOM 0-1 L0STAT Link Buffer 0 status (READ ONLY): 11=full, 00=empty, 01=reserved, 10=partially full
LCOM 2-3 L1STAT Link Buffer 1 status (READ ONLY): 11=full, 00=empty, 01=reserved, 10=partially full
LCOM 4-5 L2STAT Link Buffer 2 status (READ ONLY): 11=full, 00=empty, 01=reserved, 10=partially full
LCOM 6-7 L3STAT Link Buffer 3 status (READ ONLY): 11=full, 00=empty, 01=reserved, 10=partially full
LCOM 8-9 L4STAT Link Buffer 4 status (READ ONLY): 11=full, 00=empty, 01=reserved, 10=partially full
LCOM 10-11 L5STAT Link Buffer 5 status (READ ONLY): 11=full, 00=empty, 01=reserved, 10=partially full
LCOM 12-19   reserved
LCOM 20 LMSP Mesh multiprocessing enable (set to 0 for normal operation)
LCOM 21-22 LPATHD Mesh multiprocessing change over delay: 00=no additional delay, 01=1 additional delay, 10=2 additional delays, 11=3 additional delays
LCOM 23-25   reserved
LCOM 26 LRERR0 Receive pack error status for link buffer 0: 1=incomplete, 0=complete
LCOM 27 LRERR1 Receive pack error status for link buffer 0: 1=incomplete, 0=complete
LCOM 28 LRERR2 Receive pack error status for link buffer 0: 1=incomplete, 0=complete
LCOM 29 LRERR3 Receive pack error status for link buffer 0: 1=incomplete, 0=complete
LCOM 30 LRERR4 Receive pack error status for link buffer 0: 1=incomplete, 0=complete
LCOM 31 LRERR5 Receive pack error status for link buffer 0: 1=incomplete, 0=complete
External Port

The external port of the ADSP-21160 has been modified but should not cause a great deal of change to ADSP-2106x external port configuration code. The modifications are to the packing modes, wait mode configuration for the external memory banks, and frequency of operation of the external port. Some minor changes have been made to the control registers as well.

SYSCON Register

The ADSP-21160 external port width is increased from 48 bits to 64 bits. This difference causes a change in the packing modes of the external port. The HPM (host packing mode) field of the SYSCON register is extended by one bit to accommodate the additional packing modes. Also, two new control bits (DCPR and LDCPR) have been added to the SYSCON register. These changes cause a shift in the other control bits of this register. Table 8 summarizes the bit location and description of the control bits in the SYSCON register.

Table 8. SYSCON Control Register
Register Bit # Name Description
SYSCON 0 SRST Software Reset
SYSCON 1 BSO Boot Select Override
SYSCON 2 IIVT Internal Interrupt Vector Table (no bootÓ mode)
SYSCON 3 IWT Instruction Word Transfer; 0=data, 1=instruction
SYSCON 4-6 HPM Host Packing Mode; 000=no packing, 001=16-48, 010=16-64, 011=32-48, 100=32-64
SYSCON 7 HMSWF Host Packing Order - MSW First; 1=MSW First, 0=LSW First
SYSCON 8 HPFLSH Host Packing Status Flush
SYSCON 9 IMDW0 Internal Memory Block 0 Data Width; 0=32-bit data, 1=40-bit data
SYSCON 10 IMDW1 Internal Memory Block 1 Data Width; 0=32-bit data, 1=40-bit data
SYSCON 11 ADREDY Active Drive REDY; 0=open drain (o/d), 1=active drive (a/d)
SYSCON 12-15 MSIZE External Memory Bank Size; MSIZE=log2(bank size)-13
SYSCON 16 BHD Buffer Hang Disable; 0=enable, 1=disable
SYSCON 17-18 EBPR External Bus Priority; 00=even, 01=core processor, 10=I/O processor
SYSCON 19 DCPR DMA Channel 10-13 Priority; 1=rotating, 0=fixed
SYSCON 20 LDCPR DMA Channel 4-9 Priority; 1=rotating, 0=fixed
SYSCON 21 PRROT Link Port/Ext. Port Priority; 1=rotating, 0=fixed
SYSCON 22-27   reserved
SYSCON 28 IMGR Internal Memory Grouping (for mesh multiprocessing)
SYSCON 29-31   reserved

Pay close attention to the new Host Packing Mode (HPM) field if your system is connected to a host. The packing modes have changed significantly to support the 64-bit bus. You may need to modify code that configures the SHARC for a specific host bus width to accommodate these changes.

WAIT (EPCON) Register

There have been significant modifications to the control register for setting the external memory bank wait modes and wait states. The name of this control register changes from WAIT to EPCON on the ADSP-21160 to more appropriately reflect its function (external port configuration). Additional functionality has been added to enable better control of the external port clock rate. The number of modes for external wait states has been reduced from five to two.

The symbol definition file (def21160.h) supports both names (WAIT or EPCON) so instructions that read/write the WAIT register explicitly will not change as far as the control register naming convention is concerned. However, specific control words written to this register as well as bit position manipulation instructions will have to be modified accordingly.

The external memory bank access configuration for the ADSP-21160 differs significantly from that of the ADSP-2106x. In general, some of the asynchronous flexibility of the ADSP-2106x has been restricted to improve the synchronous behavior of the interface. The ADSP-21160 always operates in the mode requiring both internal wait states and external acknowledge (ACK) for all memory banks.

The external port of the ADSP-21160 supports new features for external memory interfacing. This interface includes support for burst transfer and pipeline transfers. Refer to the External Memory Interface chapter of the ADSP-21160 SHARC specification for specific information on these new features.

External Port Frequency

The ADSP-21160 uses an on-chip phase-locked loop to generate its internal clock, which is a multiple of the CLKIN (clock input) frequency. Note that the external port of the ADSP-21160 operates at the same frequency of the CLKIN signal. Therefore, the memory interface timing will be with respect to CLKIN and not to the core frequency. This has significant effects on the wait mode configurations. The system design section of the ADSP-21160 SHARC specification should be referenced for more detail on this subject.

Developing Code for the ADSP-21160 Using VisualDSP 4.0

Because the ADSP-21160 is based on the ADSP-21060 architecture and was developed to be code compatible with this first generation SHARC, it is possible to do a great deal of software development for the ADSP-21160 using release 4.0 of VisualDSP. An upgrade to the VisualDSP 4.0 tools with support for the SIMD SHARC's architecture will soon be available. Until these tools are available, code development can be accomplished using VisualDSP 4.0.

Memory Map

The memory map for the ADSP-21160 is not supported in the 4.0 release of VisualDSP. Use a memory map for the ADSP-21060 to develop code using this release. The linker supports include files in linker description files (LDF), facilitating the process of translating to the ADSP-21160 optimized development tools when available. The memory map for the ADSP-21060 (for development with VisualDSP 4.0) should be defined in a text file that uses an include file in the memory description section of the LDF file. The memory map for the ADSP-21160, using the same segment names as in the ADSP-21060 memory description file, should be defined in a separate text file. When porting code to the ADSP-21160, modify the LDF file to use the include file with the memory description section for the ADSP-21160 file and change the architecture name to ADSP-21160.

An example LDF file (21160.ldf) for the ADSP-21160 appears at the end of this application note. It uses a #include statement for the memory map of the system and is followed by two text files (mem21160.h and mem21060.h) that describe the internal memory map of the ADSP-21160 and the ADSP-21060 respectively. They can be used as described above.

Symbol Definitions

All ADSP-21160 code should be developed using a symbol definition file for the ADSP-21060 (def21060.h). This facilitates the porting of code to the ADSP-21160. Simply change the #include statement for the symbol definition file to include the symbol definition file which supports the ADSP-21160 (def21160.h).

Note: the symbol definition file (def21160.h) is based on preliminary technical data and is subject to change. Updates will be posted on the Analog Devices FTP site:


The ADSP-21160 was designed to be assembly code compatible with the first generation of the SHARC family of DSPs. This application note outlines the minor modifications necessary to port code from the ADSP-2106x to the ADSP-21160. This process is straight forward. By using the example symbol definition file (Listing 1 on page 17), runtime header file (Listing 2 on page 23), and linker description file (Listing 3 on page 24 and Listing 4 on page 25), you should not have difficulty porting code to the ADSP-21160, preserving your development investment and achieving a major performance increase in code execution.

Listing 1. Def21160.h Symbol File

/* -----------------------------------------------------------------------------

DEF21160.H - symbol definition file for the 21160 system and IOP register bit and address definitions for the ADSP-2116x

Last Modification on: June-12-98

Note: This file is based on preliminary technical data and is subject to change. Updates will be posted on the Analog Devices FTP site:

This include file contains a list of macro defines to enable the programmer to use symbolic names for all of the system register bits for the ADSP-2116x. It also contains macros for the IOP register addresses and some bit fields. Here are some example uses:

bit set mode1 BR0|IRPTEN|ALUSTAT;




/* MODE1 and MMASK registers */

#define BR8 0x00000001 /* Bit 0: Bit-reverse for I8 */

#define BR0 0x00000002 /* Bit 1: Bit-reverse for I0 (uses DMS0-only) */

#define SRCU 0x00000004 /* Bit 2: Alt. register select for comp. units */

#define SRD1H 0x00000008 /* Bit 3: DAG1 alt. register select (7-4) */

#define SRD1L 0x00000010 /* Bit 4: DAG1 alt. register select (3-0) */

#define SRD2H 0x00000020 /* Bit 5: DAG2 alt. register select (15-12) */

#define SRD2L 0x00000040 /* Bit 6: DAG2 alt. register select (11-8) */

#define SRRFH 0x00000080 /* Bit 7: Register file alt. select for R(15-8) */

#define SRRFL 0x00000400 /* Bit 10: Register file alt. select for R(7-0) */

#define NESTM 0x00000800 /* Bit 11: Interrupt nesting enable */

#define IRPTEN 0x00001000 /* Bit 12: Global interrupt enable */

#define ALUSAT 0x00002000 /* Bit 13: Enable ALU fixed-pt. saturation */

#define SSE 0x00004000 /* Bit 14: Enable short word sign extension */

#define TRUNC 0x00008000 /* Bit 15: 1=fltg-pt. trunc. 0=Rnd to nearest */

#define RND32 0x00010000 /* Bit 16: 1=32-bit fltg-pt. rnd 0=40-bit rnd */

#define CSEL 0x00060000 /* Bit 17-18: CSelect: Bus Mastership */

#define PEYEN 0x00200000 /* Bit 21: Processing Element Y enable */

#define SIMD 0x00200000 /* Bit 21: Enable SIMD Mode */

#define BDCST9 0x00400000 /* Bit 22: Load Broadcast for I9 */

#define BDCST1 0x00800000 /* Bit 23: Load Broadcast for I1 */

#define CBUFEN 0x01000000 /* Bit 24: Circular Buffer Enable */

/* MODE2 register */

#define IRQ0E 0x00000001 /* Bit 0: IRQ0- 1=edge sens. 0=level sens. */

#define IRQ1E 0x00000002 /* Bit 1: IRQ1- 1=edge sens. 0=level sens. */

#define IRQ2E 0x00000004 /* Bit 2: IRQ2- 1=edge sens. 0=level sens. */

#define CADIS 0x00000010 /* Bit 4: Cache disable */

#define TIMEN 0x00000020 /* Bit 5: Timer enable */

#define BUSLK 0x00000040 /* Bit 6: External bus lock */

#define FLG0O 0x00008000 /* Bit 15: FLAG0 1=output 0=input */

#define FLG1O 0x00010000 /* Bit 16: FLAG1 1=output 0=input */

#define FLG2O 0x00020000 /* Bit 17: FLAG2 1=output 0=input */

#define FLG3O 0x00040000 /* Bit 18: FLAG3 1=output 0=input */

#define CAFRZ 0x00080000 /* Bit 19: Cache freeze */

/* FLAG register */

#define FLG0 0x00000001 /* Bit 0: FLAG0 value */

#define FLG1 0x00000002 /* Bit 1: FLAG1 value */

#define FLG2 0x00000004 /* Bit 2: FLAG2 value */

#define FLG3 0x00000008 /* Bit 3: FLAG3 value */

/* ASTATx and ASTATy registers */

#define AZ 0x00000001 /* Bit 0: ALU result zero or fltg-pt. underflow */

#define AV 0x00000002 /* Bit 1: ALU overflow */

#define AN 0x00000004 /* Bit 2: ALU result negative */

#define AC 0x00000008 /* Bit 3: ALU fixed-pt. carry */

#define AS 0x00000010 /* Bit 4: ALU X input sign (ABS and MANT ops) */

#define AI 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */

#define MN 0x00000040 /* Bit 6: Multiplier result negative */

#define MV 0x00000080 /* Bit 7: Multiplier overflow */

#define MU 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */

#define MI 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation */

#define AF 0x00000400 /* Bit 10: ALU fltg-pt. operation */

#define SV 0x00000800 /* Bit 11: Shifter overflow */

#define SZ 0x00001000 /* Bit 12: Shifter result zero */

#define SS 0x00002000 /* Bit 13: Shifter input sign */

#define BTF 0x00040000 /* Bit 18: Bit test flag for system registers */

#define CACC0 0x01000000 /* Bit 24: Compare Accumulation Bit 0 */

#define CACC1 0x02000000 /* Bit 25: Compare Accumulation Bit 1 */

#define CACC2 0x04000000 /* Bit 26: Compare Accumulation Bit 2 */

#define CACC3 0x08000000 /* Bit 27: Compare Accumulation Bit 3 */

#define CACC4 0x10000000 /* Bit 28: Compare Accumulation Bit 4 */

#define CACC5 0x20000000 /* Bit 29: Compare Accumulation Bit 5 */

#define CACC6 0x40000000 /* Bit 30: Compare Accumulation Bit 6 */

#define CACC7 0x80000000 /* Bit 31: Compare Accumulation Bit 7 */

/* STKYx and STKYy registers */

#define AUS 0x00000001 /* Bit 0: ALU fltg-pt. underflow */

#define AVS 0x00000002 /* Bit 1: ALU fltg-pt. overflow */

#define AOS 0x00000004 /* Bit 2: ALU fixed-pt. overflow */

#define AIS 0x00000020 /* Bit 5: ALU fltg-pt. invalid operation */

#define MOS 0x00000040 /* Bit 6: Multiplier fixed-pt. overflow */

#define MVS 0x00000080 /* Bit 7: Multiplier fltg-pt. overflow */

#define MUS 0x00000100 /* Bit 8: Multiplier fltg-pt. underflow */

#define MIS 0x00000200 /* Bit 9: Multiplier fltg-pt. invalid operation */

#define CB7S 0x00020000 /* Bit 17: DAG1 circular buffer 7 overflow */

#define CB15S 0x00040000 /* Bit 18: DAG2 circular buffer 15 overflow */

#define PCFL 0x00200000 /* Bit 21: PC stack full */

#define PCEM 0x00400000 /* Bit 22: PC stack empty */

#define SSOV 0x00800000 /* Bit 23: Status stack overflow (MODE1 and ASTAT) */

#define SSEM 0x01000000 /* Bit 24: Status stack empty */

#define LSOV 0x02000000 /* Bit 25: Loop stack overflow */

#define LSEM 0x04000000 /* Bit 26: Loop stack empty */

/* IRPTL and IMASK and IMASKP registers */

#define EMUI 0x00000001 /* Bit 0: Offset: 00: Emulator interrupt */

#define RSTI 0x00000002 /* Bit 1: Offset: 04: Reset */

#define IOPSPI 0x00000004 /* Bit 2: Offset: 08: IOP Space Accessed */

#define SOVFI 0x00000008 /* Bit 3: Offset: 0c: Stack overflow */

#define TMZHI 0x00000010 /* Bit 4: Offset: 10: Timer = 0 (high priority) */

#define VIRPTI 0x00000020 /* Bit 5: Offset: 14: Vector interrupt */

#define IRQ2I 0x00000040 /* Bit 6: Offset: 18: IRQ2- asserted */

#define IRQ1I 0x00000080 /* Bit 7: Offset: 1c: IRQ1- asserted */

#define IRQ0I 0x00000100 /* Bit 8: Offset: 20: IRQ0- asserted */

#define SPR0I 0x00000400 /* Bit 10: Offset: 28: SPORT0 receive DMA channel */

#define SPR1I 0x00000800 /* Bit 11: Offset: 2c: SPORT1 receive (or LBUF0) */

#define SPT0I 0x00001000 /* Bit 12: Offset: 30: SPORT0 transmit DMA channel */

#define SPT1I 0x00002000 /* Bit 13: Offset: 34: SPORT1 transmit (or LBUF0) */

#define LPISUMI 0x00004000 /* Bit 14: Offset: NA: Link buf. IRQ Sum */

#define EP0I 0x00008000 /* Bit 15: Offset: 50: Ext. port chan. 0 DMA */

#define EP1I 0x00010000 /* Bit 16: Offset: 54: Ext. port chan. 1 DMA */

#define EP2I 0x00020000 /* Bit 17: Offset: 58: Ext. port chan. 2 DMA */

#define EP3I 0x00040000 /* Bit 18: Offset: 5c: Ext. port chan. 3 DMA */

#define LSRQI 0x00080000 /* Bit 19: Offset: 60: Link service request */

#define CB7I 0x00100000 /* Bit 20: Offset: 64: Circ. buffer 7 overflow */

#define CB15I 0x00200000 /* Bit 21: Offset: 68: Circ. buffer 15 overflow */

#define TMZLI 0x00400000 /* Bit 22: Offset: 6c: Timer = 0 (low pri.) */

#define FIXI 0x00800000 /* Bit 23: Offset: 70: Fixed-pt. overflow */

#define FLTOI 0x01000000 /* Bit 24: Offset: 74: fltg-pt. overflow */

#define FLTUI 0x02000000 /* Bit 25: Offset: 78: fltg-pt. underflow */

#define FLTII 0x04000000 /* Bit 26: Offset: 7c: fltg-pt. invalid */

#define SFT0I 0x08000000 /* Bit 27: Offset: 80: user software int 0 */

#define SFT1I 0x10000000 /* Bit 28: Offset: 84: user software int 1 */

#define SFT2I 0x20000000 /* Bit 29: Offset: 88: user software int 2 */

#define SFT3I 0x40000000 /* Bit 30: Offset: 8c: user software int 3 */

/* LIRPTL register */

#define LP0I 0x00000001 /* Bit 0: Offset: 38: Link Buffer 0 DMA */

#define LP1I 0x00000002 /* Bit 1: Offset: 3c: Link Buffer 1 DMA */

#define LP2I 0x00000004 /* Bit 2: Offset: 40: Link Buffer 2 DMA */

#define LP3I 0x00000008 /* Bit 3: Offset: 44: Link Buffer 3 DMA */

#define LP4I 0x00000010 /* Bit 4: Offset: 48: Link Buffer 4 DMA */

#define LP5I 0x00000020 /* Bit 5: Offset: 4c: Link Buffer 5 DMA */

#define LP0MSK 0x00010000 /* Bit 16: Link Buffer 0 Interrupt Mask */

#define LP1MSK 0x00020000 /* Bit 17: Link Buffer 1 Interrupt Mask */

#define LP2MSK 0x00040000 /* Bit 18: Link Buffer 2 Interrupt Mask */

#define LP3MSK 0x00080000 /* Bit 19: Link Buffer 3 Interrupt Mask */

#define LP4MSK 0x00100000 /* Bit 20: Link Buffer 4 Interrupt Mask */

#define LP5MSK 0x00200000 /* Bit 21: Link Buffer 5 Interrupt Mask */

#define LP0MSKP 0x01000000 /* Bit 24: Link Buffer 0 Interrupt Mask Ptr */

#define LP1MSKP 0x02000000 /* Bit 25: Link Buffer 1 Interrupt Mask Ptr */

#define LP2MSKP 0x04000000 /* Bit 26: Link Buffer 2 Interrupt Mask Ptr */

#define LP3MSKP 0x08000000 /* Bit 27: Link Buffer 3 Interrupt Mask Ptr */

#define LP4MSKP 0x10000000 /* Bit 28: Link Buffer 4 Interrupt Mask Ptr */

#define LP5MSKP 0x20000000 /* Bit 29: Link Buffer 5 Interrupt Mask Ptr */

/* I/O Processor Registers */

#define SYSCON 0x00 /* System configuration register */

#define VIRPT 0x01 /* Vector interrupt register */

#define EPCON 0x02 /* Wait state configuration for external memory */

#define WAIT 0x02 /* Wait state configuration for external memory */

#define SYSTAT 0x03 /* System status register */

#define EPB0 0x04 /* External port DMA buffer 0 */

#define EPB1 0x05 /* External port DMA buffer 1 */

#define EPB2 0x06 /* External port DMA buffer 3 */

#define EPB3 0x07 /* External port DMA buffer 4 */

#define MSGR0 0x08 /* Message register 0 */

#define MSGR1 0x09 /* Message register 1 */

#define MSGR2 0x0a /* Message register 2 */

#define MSGR3 0x0b /* Message register 3 */

#define MSGR4 0x0c /* Message register 4 */

#define MSGR5 0x0d /* Message register 5 */

#define MSGR6 0x0e /* Message register 6 */

#define MSGR7 0x0f /* Message register 7 */

#define BMAX 0x18 /* Bus time-out maximum */

#define BCNT 0x19 /* Bus time-out counter */

#define ELAST 0x1b /* Address of last external access for page detect */

#define DMAC10 0x1c /* EP DMA10 control register */

#define DMAC11 0x1d /* EP DMA11 control register */

#define DMAC12 0x1e /* EP DMA12 control register */

#define DMAC13 0x1f /* EP DMA13 control register */

#define II4 0x30 /* Internal DMA4 memory address */

#define IM4 0x31 /* Internal DMA4 memory access modifier */

#define C4 0x32 /* Contains # of DMA4 transfers remaining */

#define CP4 0x33 /* Points to next DMA4 parameters */

#define GP4 0x34 /* DMA4 General purpose / 2-D DMA */

#define DB4 0x35 /* DMA4 General purpose / 2-D DMA */

#define DA4 0x36 /* DMA4 General purpose / 2-D DMA */

#define DMASTAT 0x37 /* DMA channel status register */

#define II5 0x38 /* Internal DMA5 memory address */

#define IM5 0x39 /* Internal DMA5 memory access modifier */

#define C5 0x3a /* Contains number of DMA5 transfers remaining */

#define CP5 0x3b /* Points to next DMA5 parameters */

#define GP5 0x3c /* DMA5 General purpose / 2-D DMA */

#define DB5 0x3d /* DMA5 General purpose / 2-D DMA */

#define DA5 0x3e /* DMA5 General purpose / 2-D DMA */

#define II10 0x40 /* Internal DMA10 memory address */

#define IM10 0x41 /* Internal DMA10 memory access modifier */

#define C10 0x42 /* Contains # of DMA10 transfers remaining */

#define CP10 0x43 /* Points to next DMA10 parameters */

#define GP10 0x44 /* DMA10 General purpose */

#define EI10 0x45 /* External DMA10 address */

#define EM10 0x46 /* External DMA10 address modifier */

#define EC10 0x47 /* External DMA10 counter */

#define II11 0x48 /* Internal DMA11 memory address */

#define IM11 0x49 /* Internal DMA11 memory access modifier */

#define C11 0x4a /* Contains # of DMA11 transfers remaining */

#define CP11 0x4b /* Points to next DMA11 parameters */

#define GP11 0x4c /* DMA11 General purpose */

#define EI11 0x4d /* External DMA11 address */

#define EM11 0x4e /* External DMA11 address modifier */

#define EC11 0x4f /* External DMA11 counter */

#define II12 0x50 /* Internal DMA12 memory address */

#define IM12 0x51 /* Internal DMA12 memory access modifier */

#define C12 0x52 /* Contains # of DMA12 transfers remaining */

#define CP12 0x53 /* Points to next DMA12 parameters */

#define GP12 0x54 /* DMA12 General purpose */

#define EI12 0x55 /* External DMA12 address */

#define EM12 0x56 /* External DMA12 address modifier */

#define EC12 0x57 /* External DMA12 counter */

#define II13 0x58 /* Internal DMA13 memory address */

#define IM13 0x59 /* Internal DMA13 memory access modifier */

#define C13 0x5a /* Contains # of DMA13 transfers remaining */

#define CP13 0x5b /* Points to next DMA13 parameters */

#define GP13 0x5c /* DMA13 General purpose */

#define EI13 0x5d /* External DMA13 address */

#define EM13 0x5e /* External DMA13 address modifier */

#define EC13 0x5f /* External DMA13 counter */

#define II0 0x60 /* Internal DMA0 memory address */

#define IM0 0x61 /* Internal DMA0 memory access modifier */

#define C0 0x62 /* Contains # of DMA0 transfers remaining */

#define CP0 0x63 /* Points to next DMA0 parameters */

#define GP0 0x64 /* DMA0 General purpose / 2-D DMA */

#define DB0 0x65 /* DMA0 General purpose / 2-D DMA */

#define DA0 0x66 /* DMA0 General purpose / 2-D DMA */

#define II1 0x68 /* Internal DMA1 memory address */

#define IM1 0x69 /* Internal DMA1 memory access modifier */

#define C1 0x6a /* Contains # of DMA1 transfers remaining */

#define CP1 0x6b /* Points to next DMA1 parameters */

#define GP1 0x6c /* DMA1 General purpose / 2-D DMA */

#define DB1 0x6d /* DMA1 General purpose / 2-D DMA */

#define DA1 0x6e /* DMA1 General purpose / 2-D DMA */

#define II2 0x70 /* Internal DMA2 memory address */

#define IM2 0x71 /* Internal DMA2 memory access modifier */

#define C2 0x72 /* Contains # of DMA2 transfers remaining */

#define CP2 0x73 /* Points to next DMA2 parameters */

#define GP2 0x74 /* DMA2 General purpose / 2-D DMA */

#define DB2 0x75 /* DMA2 General purpose / 2-D DMA */

#define DA2 0x76 /* DMA2 General purpose / 2-D DMA */

#define II3 0x78 /* Internal DMA3 memory address */

#define IM3 0x79 /* Internal DMA3 memory access modifier */

#define C3 0x7a /* Contains # of DMA3 transfers remaining */

#define CP3 0x7b /* Points to next DMA3 parameters */

#define GP3 0x7c /* DMA3 General purpose / 2-D DMA */

#define DB3 0x7d /* DMA3 General purpose / 2-D DMA */

#define DA3 0x7e /* DMA3 General purpose / 2-D DMA */

#define II6 0x80 /* Internal DMA6 memory address */

#define IM6 0x81 /* Internal DMA6 memory access modifier */

#define C6 0x82 /* Contains # of DMA6 transfers remaining */

#define CP6 0x83 /* Points to next DMA6 parameters */

#define GP6 0x84 /* DMA6 General purpose / 2-D DMA */

#define DB6 0x85 /* DMA6 General purpose / 2-D DMA */

#define DA6 0x86 /* DMA6 General purpose / 2-D DMA */

#define II7 0x88 /* Internal DMA7 memory address */

#define IM7 0x89 /* Internal DMA7 memory access modifier */

#define C7 0x8a /* Contains # of DMA7 transfers remaining */

#define CP7 0x8b /* Points to next DMA7 parameters */

#define GP7 0x8c /* DMA7 General purpose / 2-D DMA */

#define DB7 0x8d /* DMA7 General purpose / 2-D DMA */

#define DA7 0x8e /* DMA7 General purpose / 2-D DMA */

#define II8 0x90 /* Internal DMA8 memory address */

#define IM8 0x91 /* Internal DMA8 memory access modifier */

#define C8 0x92 /* Contains # of DMA8 transfers remaining */

#define CP8 0x93 /* Points to next DMA8 parameters */

#define GP8 0x94 /* DMA8 General purpose / 2-D DMA */

#define DB8 0x95 /* DMA8 General purpose / 2-D DMA */

#define DA8 0x96 /* DMA8 General purpose / 2-D DMA */

#define II9 0x98 /* Internal DMA9 memory address */

#define IM9 0x99 /* Internal DMA9 memory access modifier */

#define C9 0x9a /* Contains # of DMA9 transfers remaining */

#define CP9 0x9b /* Points to next DMA9 parameters */

#define GP9 0x9c /* DMA9 General purpose / 2-D DMA */

#define DB9 0x9d /* DMA9 General purpose / 2-D DMA */

#define DA9 0x9e /* DMA9 General purpose / 2-D DMA */

#define LBUF0 0xc0 /* Link buffer 0 */

#define LBUF1 0xc1 /* Link buffer 1 */

#define LBUF2 0xc2 /* Link buffer 2 */

#define LBUF3 0xc3 /* Link buffer 3 */

#define LBUF4 0xc4 /* Link buffer 4 */

#define LBUF5 0xc5 /* Link buffer 5 */

#define LCTL0 0xc6 /* Link buffer control */

#define LCTL1 0xc7 /* Link buffer control */

#define LCOM 0xc8 /* Link common control */

#define LAR 0xc9 /* Link assignment register */

#define LSRQ 0xca /* Link service request and mask register */

#define LPATH1 0xcb /* Link path register 1 */

#define LPATH2 0xcc /* Link path register 2 */

#define LPATH3 0xcd /* Link path register 3 */

#define LPCNT 0xce /* Link path counter */

#define CNST1 0xcf /* Link port constant 1 register */

#define CNST2 0xd0 /* Link port constant 2 register */

#define STCTL0 0xe0 /*Serial Port 0 Transmit Control Register */

#define SRCTL0 0xe1 /*Serial Port 0 Receive Control Register */

#define TX0 0xe2 /*Serial Port 0 Transmit Data Buffer */

#define RX0 0xe3 /*Serial Port 0 Receive Data Buffer */

#define TDIV0 0xe4 /*Serial Port 0 Transmit Divisor */

#define TCNT0 0xe5 /*Serial Port 0 Transmit Count Reg */

#define RDIV0 0xe6 /*Serial Port 0 Receive Divisor */

#define RCNT0 0xe7 /*Serial Port 0 Receive Count Reg */

#define MTCS0 0xe8 /*Serial Port 0 Mulitchannel Transmit Selector */

#define MRCS0 0xe9 /*Serial Port 0 Mulitchannel Receive Selector */

#define MTCCS0 0xea /*Serial Port 0 Mulitchannel Transmit Selector */

#define MRCCS0 0xeb /*Serial Port 0 Mulitchannel Receive Selector */

#define SPATH0 0xee /*Serial Port 0 Path Length (Mesh Multiprocessing) */

#define SPCNT0 0xef /*Serial Port 0 Path Counter (Mesh Multiprocessing) */

#define STCTL1 0xf0 /*Serial Port 1 Transmit Control Register */

#define SRCTL1 0xf1 /*Serial Port 1 Receive Control Register */

#define TX1 0xf2 /*Serial Port 1 Transmit Data Buffer */

#define RX1 0xf3 /*Serial Port 1 Receive Data Buffer */

#define TDIV1 0xf4 /*Serial Port 1 Transmit Divisor */

#define TCNT1 0xf5 /*Serial Port 1 Transmit Count Reg */

#define RDIV1 0xf6 /*Serial Port 1 Receive Divisor */

#define RCNT1 0xf7 /*Serial Port 1 Receive Count Reg */

#define MTCS1 0xf8 /*Serial Port 1 Mulitchannel Transmit Selector */

#define MRCS1 0xf9 /*Serial Port 1 Mulitchannel Receive Selector */

#define MTCCS1 0xfa /*Serial Port 1 Mulitchannel Transmit Selector */

#define MRCCS1 0xfb /*Serial Port 1 Mulitchannel Receive Selector */

#define SPATH1 0xfe /*Serial Port 1 Path Length (Mesh Multiprocessing) */

#define SPCNT1 0xff /*Serial Port 1 Path Counter (Mesh Multiprocessing) */

/* SYSCON Register */

#define SRST 0x00000001 /* Soft Reset */

#define BSO 0x00000002 /* Boot Select Override */

#define IIVT 0x00000004 /* Internal Interrupt Vector Table */

#define IWT 0x00000008 /* Instruction word xfer (0=data, 1=inst) */

#define HPM000 0x00000000 /* Host packing mode: None */

#define HPM001 0x00000010 /* Host packing mode: 16/48 */

#define HPM010 0x00000020 /* Host packing mode: 16/64 */

#define HPM011 0x00000030 /* Host packing mode: 32/48 */

#define HPM100 0x00000040 /* Host packing mode: 32/64 */

#define HMSWF 0x00000080 /* Host pack order (0=LSW first, 1=MSW) */

#define HPFLSH 0x00000100 /* Host pack flush */

#define IMDW0X 0x00000200 /* Int. mem. block 0, extended data (40 bit) */

#define IMDW1X 0x00000400 /* Int. mem. block 1, extended data (40 bit) */

#define ADREDY 0x00000800 /* Active Drive REDY */

#define BHD 0x00010000 /* Buffer Hang Disable */

#define EBPR00 0x00000000 /* External bus priority: Even */

#define EBPR01 0x00020000 /* External bus priority: Core has priority */

#define EBPR10 0x00040000 /* External bus priority: IO has priority */

#define DCPR 0x00080000 /* Select rot. priority on DMA10 - DMA13 */

#define LDCPR 0x00100000 /* Select rot. priority on DMA4 - DMA9 */

#define PRROT 0x00200000 /* Select rot. priority LPORT/EPORT */

/* SYSTAT Register */

#define HSTM 0x00000001 /* Host is the Bus Master */

#define BSYN 0x00000002 /* Bus arbitration logic is synchronized */

#define CRBM 0x00000070 /* Current ADSP2116x Bus Master */

#define IDC 0x00000700 /* ADSP2116x ID Code */

#define DWPD 0x00001000 /* Direct write pending (0=none, 1=pend) */

#define VIPD 0x00002000 /* Vector interrupt pending (1 = pending) */

#define HPS 0x0000c000 /* Host pack status */

/* WAIT or EPCON Register */

#define EB0BE 0x00000001 /* External Bank 0 Burst Enable (if 1 wait) */

#define EB0IE 0x00000002 /* External Bank 0 Idle Cycle Enable */

#define EB1BE 0x00000020 /* External Bank 1 Burst Enable (if 1 wait) */

#define EB1IE 0x00000040 /* External Bank 1 Idle Cycle Enable */

#define EB2BE 0x00000400 /* External Bank 2 Burst Enable (if 1 wait) */

#define EB2IE 0x00000800 /* External Bank 2 Idle Cycle Enable */

#define EB3BE 0x00008000 /* External Bank 3 Burst Enable (if 1 wait) */

#define EB3IE 0x00010000 /* External Bank 3 Idle Cycle Enable */

#define UBBE 0x00100000 /* Unbanked Burst Enable (if 1 wait) */

#define UBIE 0x00200000 /* Unbanked Idle Cycle Enable */

#define PAGEIS 0x10000000 /* 1 idle cyc. on DRAM page bound. cross */

#define MMSWS 0x20000000 /* Single wait state for MMS access */

#define HIDMA 0x80000000 /* Single idle cycle for DMA handshake */

Listing 2. IVT.ASM ADSP-21160 Runtime Header File



/* IVT.asm Assembly runtime header for interrupt vector table of the ADSP-2116x */

/* Program memory segment for interrupt vector table */

.extern main; /* Beginning of application program */

.SEGMENT/PM isr_tabl; /* Interrupt Service Table */

emulator: NOP; NOP; NOP; NOP; /* Reserved interrupt vector for emulator; do not place code here */

rst_svc: IDLE; /* Vector for reset: */

jump main; /* used by loader during final initialization */



iiopai_svc: RTI; RTI; RTI; RTI; /* Vector for illegal IOP register space access: */

sovfi_svc: RTI; RTI; RTI; RTI; /* V. for status/loop stack overflow or PC stack full */

tmzhi_svc: RTI; RTI; RTI; RTI; /* Vector for high priority timer interrupt: */

virpti_svc: RTI; RTI; RTI; RTI; /* Vector for vectored interrupt: */

irq2_svc: RTI; RTI; RTI; RTI;/* Vector for external interrupt 2: */

irq1_svc: RTI; RTI; RTI; RTI; /* Vector for external interrupt 1: */

irq0_svc: RTI; RTI; RTI; RTI; /* Vector for external interrupt 0: */

Reserved1: NOP; NOP; NOP; NOP; /* Reserved interrupt vector */

spr0_svc: RTI; RTI; RTI; RTI; /* Vectors for Serial port DMA channels: */

spr1_svc: RTI; RTI; RTI; RTI;

spt0_svc: RTI; RTI; RTI; RTI;

spt1_svc: RTI; RTI; RTI; RTI;

lb0_svc: RTI; RTI; RTI; RTI; /* Vectors for link buffer DMA channels: */

lb1_svc: RTI; RTI; RTI; RTI;

lb2_svc: RTI; RTI; RTI; RTI;

lb3_svc: RTI; RTI; RTI; RTI;

lb4_svc: RTI; RTI; RTI; RTI;

lb5_svc: RTI; RTI; RTI; RTI;

ep0_svc: RTI; RTI; RTI; RTI; /* Vectors for External port DMA channels: */

ep1_svc: RTI; RTI; RTI; RTI;

ep2_svc: RTI; RTI; RTI; RTI;

ep3_svc: RTI; RTI; RTI; RTI;

lsrq_svc: RTI; RTI; RTI; RTI; /* Vector for Link service request: */

cb7_svc: RTI; RTI; RTI; RTI; /* Vector for DAG1 pointer 7 circular buffer overflow: */

cb15_svc: RTI; RTI; RTI; RTI; /* Vector for DAG2 pointer 15 circular buffer overflow: */

tmzl_svc: RTI; RTI; RTI; RTI; /* Vector for lower priority timer interrupt: */

fixi_svc: RTI; RTI; RTI; RTI; /* Vector for fixed point overflow interrupt: */

fltoi_svc: RTI; RTI; RTI; RTI; /* Vector for floating point overflow interrupt: */

fltui_svc: RTI; RTI; RTI; RTI; /* Vector for floating point underflow interrupt: */

fltii_svc: RTI; RTI; RTI; RTI; /* Vector for floating point invalid interrupt: */

sft0i_svc: RTI; RTI; RTI; RTI; /* Vector for user software 0 interrupt: */

sft1i_svc: RTI; RTI; RTI; RTI; /* Vector for user software 1 interrupt: */

sft2i_svc: RTI; RTI; RTI; RTI; /* Vector for user software 2 interrupt: */

sft3i_svc: RTI; RTI; RTI; RTI; /* Vector for user software 3 interrupt: */

Reserved2: NOP; NOP; NOP; NOP; /* Reserved interrupt vector: */


Listing 3. 21160.ldf Linker Description File

// 21160.ldf

// Linker Description File for the 21160



// ADSP-21160 Memory Map:

// ------------------------------------------------

// Internal memory 0x0000 0000 to 0x0007 ffff

// ------------------------------------------------

// 0x0000 0000 to 0x0000 00ff IOP Regs

// 0x0000 0100 to 0x0001 ffff (reserved)

// Block 0 0x0002 0000 to 0x0002 7fff Long Word (64) Addresses

// Block 1 0x0002 8000 to 0x0002 ffff Long Word (64) Addresses

// 0x0003 0000 to 0x0003 ffff (reserved)

// Block 0 0x0004 0000 to 0x0004 ffff Normal Word (32/48) Addresses

// Block 1 0x0005 0000 to 0x0005 ffff Normal Word (32/48) Addresses

// 0x0006 0000 to 0x0007 ffff (reserved)

// Block 0 0x0008 0000 to 0x0009 ffff Short Word (16) Addresses

// Block 1 0x000A 0000 to 0x000B ffff Short Word (16) Addresses

// 0x000C 0000 to 0x000f ffff (reserved)

// ------------------------------------------------

// Multiproc memory 0x0010 0000 to 0x007f ffff

// ------------------------------------------------

// 0x0010 0000 to 0x001f ffff SHARC ID=001 Internal memory

// 0x0020 0000 to 0x002f ffff SHARC ID=010 Internal memory

// 0x0030 0000 to 0x003f ffff SHARC ID=011 Internal memory

// 0x0040 0000 to 0x004f ffff SHARC ID=100 Internal memory

// 0x0050 0000 to 0x005f ffff SHARC ID=101 Internal memory

// 0x0060 0000 to 0x006f ffff SHARC ID=110 Internal memory

// 0x0070 0000 to 0x007f ffff SHARC ID=all Internal memory

// ------------------------------------------------

// External memory 0x0080 0000 to 0xffff ffff

// ------------------------------------------------


$LIBRARIES = lib060.dlb;



// Memory architecture description for this example on a ADSP-21160.

// 256 48-bit words for interrupt vector table (reset vector location).

// 1792 48-bit words of program memory for code storage.

// 20k 32-bit words of program memory for data storage.

// 64k 32-bit words of data memory for data storage.


{INCLUDE ("mem21160.h")} // End MEMORY



LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) // Other object files to link against.

OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) // Resulting executable file name.



// Map the sections specified in the program files to sections declared in

// MEMORY and use these sections to create the object file for processor p0.




} >isr_tabl




} >bk0_code




} >bk0_data




} >bk1_data


} // End p0

Listing 4. Mem21160.h Memory Description For Linker Description File

// mem21160.h

isr_tabl { TYPE(PM RAM) START(0x00040000) END(0x000400ff) WIDTH(48) }

bk0_code { TYPE(PM RAM) START(0x00040100) END(0x000407ff) WIDTH(48) }

bk0_data { TYPE(PM RAM) START(0x00043000) END(0x00047fff) WIDTH(32) }

bk1_data { TYPE(DM RAM) START(0x00050000) END(0x0005ffff) WIDTH(32) }

// mem21060.h

isr_tabl { TYPE(PM RAM) START(0x00020000) END(0x000200ff) WIDTH(48) }

bk0_code { TYPE(PM RAM) START(0x00020100) END(0x000207ff) WIDTH(48) }

bk0_data { TYPE(PM RAM) START(0x00023000) END(0x00027fff) WIDTH(32) }

bk1_data { TYPE(DM RAM) START(0x00030000) END(0x0003ffff) WIDTH(32) }

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