|Chapter: 3||Page: 39|
|DOC ID: DOC-711|
|Because only the timer interrupt on the TMZHI bit pushes the status stack (as described on page 11-9), the paragraph following step 2 of the "To process an interrupt" process needs to change from: |
If the interrupt is an external interrupt (IRQ2-0), the internal timer interrupt, or the VIRPT multiprocessor vector interrupt, the Program Sequencer pushes the current value of the ASTAT and MODE1 registers onto the status stack.
If the interrupt is an external interrupt (IRQ2-0), the timer interrupt TMZHI (see Timer Interrupts and the Status Stack on page 11-9), or the VIRPT multiprocessor vector interrupt, the Program Sequencer pushes the current value of the ASTAT and MODE1 registers onto the status stack.
|Chapter: 6||Page: 39|
|DOC ID: DOC-667|
|Add the following sentence at the beginning of the last paragraph on the page (When chaining is enabled, DMA transfers are initiated by writing a memory address to the CP register. ...). Add: |
Chain pointer register should be cleared first before enabling chaining.
This sentence also should be inserted as a cautionary note before the last paragraph on page 6-43 (Before starting the first transfer, ...).
|Chapter: 9||Page: 61|
|DOC ID: DOC-641|
|In the I2S Mode section following the second paragraph (The I2S bus ... and the right channel.), add the following information bullet:
SHARC SPORTs are designed such that in I2S master mode, LRCLK is held at the last driven logic level and does not transition, to provide an edge, after the final data word is driven out. Therefore, while transmitting a fixed number of words to an I2S receiver that expects an LRCLK edge to receive the incoming data word, the SPORT should send a dummy word after transmitting the fixed number of words. The transmission of this dummy word toggles LRCLK, generating an edge. Transmission of the dummy word is not required when the I2S receiver is a SHARC SPORT.
|Chapter: 12||Page: 52|
|DOC ID: DOC-627|
|For clarity, change the wording of the section title.
Bootstraping (256 instructions)
Bootstrap Loading from EPROM (256 instructions)
|Chapter: A||Page: 95|
|DOC ID: DOC-692|
|Add the following information to the PUSH instruction description as a note: |
When a PUSH LOOP instruction is executed, top of the loop address stack is filled with zero. After executing the PUSH LOOP instruction, LADDR must be written with the content which is to be pushed on the loop address stack. A write to the LADDR will update the top of the loop address stack.
|Chapter: n/a||Page: 1|
|DOC ID: DOC-577|
|In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.|
In the Preface, the IP address of the FTP server is no longer valid. Use ftp://188.8.131.52 instead.