Documentation Errata for ADSP-21161 SHARC Processor Hardware Reference (Revision 4.0, February 2005)

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• The PM data bus is 64-bits wide.
• The DM data bus is 64-bits wide.
• The PM address bus width is 32-bits wide.

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If an interrupt recurs while its service routine is running and nesting is enabled, the processor updates IRPTL, but does not service the interrupt. The processor waits until the return from interrupt (RTI) completes before vectoring to the service routine again.

If an interrupt recurs while its service routine is running and nesting is enabled, the processor does not update IRPTL. For programs to re-use the same interrupt from within its own ISR, use the JUMP(CI) instruction.

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/*________start of DMA initialization routine__________*/
.SECTION/PMpm_code;
int_to_ext_memory_chainDMA:
r0=source;
dm(tcb + 7) = r0; /* Write Source1 address to II tcb_a */
r0=dest;
dm(tcb + 2) = r0; /* Write Dest1 address to EI slot in tcb_a */
r0=tcb + 7;
r1= b#10000000000000000000;
r0=r0 or r1;/* set PCI Bit */
dm(tcb + 4) = r0; /* Write tcb address to CP slot in tcb */

r0 = 0; /* Clear CP register before enabling chaining */
dm(CPEP0) = r0;

r0=0;
dm(DMAC10)=r0; /* Clear DMA Control Register */
r0=b#00000000000000000000010100000111;
dm(DMAC10)=r0; /* dma enable, Chain enable,int>ext, master mode */
r0=tcb + 7;
dm(CPEP0) =r0; /* Load CP register*/
bit set imask EP0I;
rts;

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/*_____________________Main Routine________________________*/
.section/pm seg_pmco;/*Main code section described in .ldf file*/
start:
ustat1 = dm(SYSCON);
bit clr ustat1 BHD; /*Disable Buffer Hang*/
dm(SYSCON) = ustat1;
imask = 0; /*Clear IMASK and IRPTL registers*/
irptl = 0;
bit set imask LPISUMI; /*Enable Link port interrupts*/
bit set lirptl LP1MSK; /*Enable Link port 1 interrupt*/
bit set mode1 IRPTEN; /*Enable global interrupts*/
r0 = 0; dm(LCTL) = r0;
r0 = 0; /* Clear CP registers before enabling chaining */
dm(CPLB0) = r0;
dm(CPLB1) = r0;

ustat1=dm(LCTL);
/*LCTL REGISTER-->LBUF0=TX, LBUF1=RX, 2x CLK RATE, LBUF 0 & 1 ENABLED, LBUF 0 & 1 -> PORT 0 DMA Enabled, DMA Chain Enabled*/
bit clr ustat1 L0TRAN | LAB0 | LAB1 | L0CLKD0 | L1CLKD0;
bit set ustat1 L1TRAN | L1EN | L0EN | L0CLKD1 | L1CLKD1 | L0DEN | L1DEN | L0CHEN | L1CHEN;

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/*-----------------Main Routine----------------------------*/
.section/pm seg_pmco;
start:
ustat3=dm(SYSCON);
bit clr ustat3 BHD; /*Disable Buffer Hang*/
dm(SYSCON)=ustat3;
bit set imask SP0I |SP2I; /*Unmask SPORT 0 & 2 Interrupts*/
bit set mode1 CBUFEN | IRPTEN; /*Enable Circ Buffers & Interupts*/
r0 = 0x00001000;
/*Set the SPL bit in the SPxxMCTL register to enable loopback*/
dm(SP02MCTL)=r0;
r0 = 0x0; /*Externally generated clock and framesync*/
dm(DIV0) = r0;
r0 = 0; /* Clear CP registers before enabling chaining */
dm(CP0A) = r0;
dm(CP2A) = r0;
r0 = 0x000c21f1;
/*Set bits SPEN_A, SLEN0-4, FSR--enable the A channel, set the word length to 32 bits, require frame synch, and enable DMA and DMA Chaining.*/
dm(SPCTL0)=r0;

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Host accesses require the address lines (AD17, AD18, AD19, and AD20) to be sampled "low" by the SHARC processor. It is not enough to just tie these address pins low to ground for host accesses; these lines must be driven low with a strong enough drive strength to overcome the keeper latches present on these pins. If the drive strength provided by the host to the SHARC processor is not strong enough, failure can occur during host accesses resulting in processor core Hang. Using a scope, it can be seen that the HBG (Host Bus Grant) toggles even when the HBR (Host Bus Request) is kept asserted during the failure.

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The I²S bus transmits audio data and control signals over separate lines. The data line carries two multiplexed data channels: the left channel and the right channel. In I²S mode, if both channels on a SPORT are set up to transmit, then SPORT transmit channels (TXxA and TXxB) transmit simultaneously, each transmitting left and right I²S channels. If both channels on a SPORT are set up to receive, the SPORT receive channels (RXxA and RXxB) receive simultaneously, each receiving left and right I²S channels. Data is transmitted in MSB format.

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In multichannel mode, the SCLKx2 and SCLKx3 pin is an input and is internally connected to its corresponding SCLKx0 and SCLKx1 pins. It is not necessary to externally connect SCLKx2 to SCLKx0 and SCLKx1 to SCLKx3.

In multichannel mode, the SCLK2 and SCLK3 pins are inputs and are internally connected to their corresponding SCLK0 and SCLK1 pins. It is not necessary to externally connect SCLK2 to SCLK0 and connect SCLK1 to SCLK3.

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ALU Floating-Point Underflow. A sticky indicator for the ALU AS bit.

ALU Floating-Point Underflow. A sticky indicator for the ALU AZ bit.

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