Documentation Errata for ADSP-21161 SHARC Processor Hardware Reference (Revision 4.0, February 2005)


Chapter:  1 Page: 21
DOC ID: DOC-575
Change

In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.

In the Preface, the IP address of the FTP server is no longer valid. Use ftp://137.71.25.69 instead.


back to top


Chapter:  3 Page: 4
DOC ID: DOC-628
Change
In Figure 3-2 (Sequencer Block Diagram), the sizes of data being read from the data buses and the size of the address being written to the address bus are labelled, but the sizes of the busses themselves are not labelled.

Update this figure, adding the following sizes to the busses:
  • The PM data bus is 64-bits wide.
  • The DM data bus is 64-bits wide.
  • The PM address bus width is 32-bits wide.

Also, changes the data read size from the PM data bus to "48", indicating a 48-bit instruction being read by the instruction cache.

back to top


Chapter:  3 Page: 47
DOC ID: DOC-625
Change
Change from:
If an interrupt recurs while its service routine is running and nesting is enabled, the processor updates IRPTL, but does not service the interrupt. The processor waits until the return from interrupt (RTI) completes before vectoring to the service routine again.

Change to:
If an interrupt recurs while its service routine is running and nesting is enabled, the processor does not update IRPTL. For programs to re-use the same interrupt from within its own ISR, use the JUMP(CI) instruction.

back to top


Chapter:  6 Page: 80
DOC ID: DOC-668
Change
In listing 6-2 (External Port Chained DMA Example), add the BOLD lines of code to the DMA initialization routine:

/*________start of DMA initialization routine__________*/
.SECTION/PMpm_code;
int_to_ext_memory_chainDMA:
r0=source;
dm(tcb + 7) = r0; /* Write Source1 address to II tcb_a */
r0=dest;
dm(tcb + 2) = r0; /* Write Dest1 address to EI slot in tcb_a */
r0=tcb + 7;
r1= b#10000000000000000000;
r0=r0 or r1;/* set PCI Bit */
dm(tcb + 4) = r0; /* Write tcb address to CP slot in tcb */

r0 = 0; /* Clear CP register before enabling chaining */
dm(CPEP0) = r0;


r0=0;
dm(DMAC10)=r0; /* Clear DMA Control Register */
r0=b#00000000000000000000010100000111;
dm(DMAC10)=r0; /* dma enable, Chain enable,int>ext, master mode */
r0=tcb + 7;
dm(CPEP0) =r0; /* Load CP register*/
bit set imask EP0I;
rts;

back to top


Chapter:  6 Page: 92
DOC ID: DOC-669
Change
In listing 6-3 (DMA-Chained Link Loopback Example), add the BOLD lines of code.

/*_____________________Main Routine________________________*/
.section/pm seg_pmco;/*Main code section described in .ldf file*/
start:
ustat1 = dm(SYSCON);
bit clr ustat1 BHD; /*Disable Buffer Hang*/
dm(SYSCON) = ustat1;
imask = 0; /*Clear IMASK and IRPTL registers*/
irptl = 0;
bit set imask LPISUMI; /*Enable Link port interrupts*/
bit set lirptl LP1MSK; /*Enable Link port 1 interrupt*/
bit set mode1 IRPTEN; /*Enable global interrupts*/
r0 = 0; dm(LCTL) = r0;
r0 = 0; /* Clear CP registers before enabling chaining */
dm(CPLB0) = r0;
dm(CPLB1) = r0;


ustat1=dm(LCTL);
/*LCTL REGISTER-->LBUF0=TX, LBUF1=RX, 2x CLK RATE, LBUF 0 & 1 ENABLED, LBUF 0 & 1 -> PORT 0 DMA Enabled, DMA Chain Enabled*/
bit clr ustat1 L0TRAN | LAB0 | LAB1 | L0CLKD0 | L1CLKD0;
bit set ustat1 L1TRAN | L1EN | L0EN | L0CLKD1 | L1CLKD1 | L0DEN | L1DEN | L0CHEN | L1CHEN;

back to top


Chapter:  6 Page: 104
DOC ID: DOC-670
Change
In listing 6-5 (DMA-Chained Sport Loopback Example), add the BOLD lines of code.

/*-----------------Main Routine----------------------------*/
.section/pm seg_pmco;
start:
ustat3=dm(SYSCON);
bit clr ustat3 BHD; /*Disable Buffer Hang*/
dm(SYSCON)=ustat3;
bit set imask SP0I |SP2I; /*Unmask SPORT 0 & 2 Interrupts*/
bit set mode1 CBUFEN | IRPTEN; /*Enable Circ Buffers & Interupts*/
r0 = 0x00001000;
/*Set the SPL bit in the SPxxMCTL register to enable loopback*/
dm(SP02MCTL)=r0;
r0 = 0x0; /*Externally generated clock and framesync*/
dm(DIV0) = r0;
r0 = 0; /* Clear CP registers before enabling chaining */
dm(CP0A) = r0;
dm(CP2A) = r0;

r0 = 0x000c21f1;
/*Set bits SPEN_A, SLEN0-4, FSR--enable the A channel, set the word length to 32 bits, require frame synch, and enable DMA and DMA Chaining.*/
dm(SPCTL0)=r0;

back to top


Chapter:  7 Page: 44
DOC ID: DOC-654
Change
Add the following description of address lines to table 7-5 (Host Interface Signals):
Host accesses require the address lines (AD17, AD18, AD19, and AD20) to be sampled "low" by the SHARC processor. It is not enough to just tie these address pins low to ground for host accesses; these lines must be driven low with a strong enough drive strength to overcome the keeper latches present on these pins. If the drive strength provided by the host to the SHARC processor is not strong enough, failure can occur during host accesses resulting in processor core Hang. Using a scope, it can be seen that the HBG (Host Bus Grant) toggles even when the HBR (Host Bus Request) is kept asserted during the failure.

back to top


Chapter:  10 Page: 48
DOC ID: DOC-642
Change
In the I2S Mode section following the second paragraph (The I2S bus ... transmitted in MSB format.), add the following information bullet:
The I2S bus transmits audio data and control signals over separate lines. The data line carries two multiplexed data channels: the left channel and the right channel. In I2S mode, if both channels on a SPORT are set up to transmit, then SPORT transmit channels (TXxA and TXxB) transmit simultaneously, each transmitting left and right I2S channels. If both channels on a SPORT are set up to receive, the SPORT receive channels (RXxA and RXxB) receive simultaneously, each receiving left and right I2S channels. Data is transmitted in MSB format.

back to top


Chapter:  10 Page: 53
DOC ID: DOC-604
Change
The information bullet following Figure 10-12 (SPORT Multichannel Mode Pairings: SPORT0 and SPORT2, SPORT1 and SPORT3) requires some editing. Change from:
In multichannel mode, the SCLKx2 and SCLKx3 pin is an input and is internally connected to its corresponding SCLKx0 and SCLKx1 pins. It is not necessary to externally connect SCLKx2 to SCLKx0 and SCLKx1 to SCLKx3.

Change to:
In multichannel mode, the SCLK2 and SCLK3 pins are inputs and are internally connected to their corresponding SCLK0 and SCLK1 pins. It is not necessary to externally connect SCLK2 to SCLK0 and connect SCLK1 to SCLK3.

back to top


Chapter:  12 Page: 11
DOC ID: DOC-594
Change
In Table 12-3 (Emulation Control Register (EMUCTL) Definition), the address in the bit 34 (NOBOOT) description is incorrect. Change "0x0080 0004" to "0x0020 0004".

back to top


Chapter: A Page: 19
DOC ID: DOC-938
Change
In table A-5 (STKYx and STKYy Register Bit Descriptions), the description of the AUS bit is not correct. Change from:
ALU Floating-Point Underflow. A sticky indicator for the ALU AS bit.
Change to:
ALU Floating-Point Underflow. A sticky indicator for the ALU AZ bit.

back to top


Last Updated: September 22, 2014
沪ICP备09046653号
Send Feedback X
content here.
content here.

Send Feedback

Close