|Chapter: 1||Page: 21|
|DOC ID: DOC-575|
|In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.|
In the Preface, the IP address of the FTP server is no longer valid. Use ftp://126.96.36.199 instead.
|Chapter: 3||Page: 4|
|DOC ID: DOC-628|
|In Figure 3-2 (Sequencer Block Diagram), the sizes of data being read from the data buses and the size of the address being written to the address bus are labelled, but the sizes of the busses themselves are not labelled.|
Update this figure, adding the following sizes to the busses:
Also, changes the data read size from the PM data bus to "48", indicating a 48-bit instruction being read by the instruction cache.
|Chapter: 3||Page: 47|
|DOC ID: DOC-625|
If an interrupt recurs while its service routine is running and nesting is enabled, the processor updates IRPTL, but does not service the interrupt. The processor waits until the return from interrupt (RTI) completes before vectoring to the service routine again.
If an interrupt recurs while its service routine is running and nesting is enabled, the processor does not update IRPTL. For programs to re-use the same interrupt from within its own ISR, use the JUMP(CI) instruction.
|Chapter: 6||Page: 80|
|DOC ID: DOC-668|
|In listing 6-2 (External Port Chained DMA Example), add the BOLD lines of code to the DMA initialization routine: |
|Chapter: 6||Page: 92|
|DOC ID: DOC-669|
|In listing 6-3 (DMA-Chained Link Loopback Example), add the BOLD lines of code. |
|Chapter: 6||Page: 104|
|DOC ID: DOC-670|
|In listing 6-5 (DMA-Chained Sport Loopback Example), add the BOLD lines of code. |
|Chapter: 7||Page: 44|
|DOC ID: DOC-654|
|Add the following description of address lines to table 7-5 (Host Interface Signals): |
Host accesses require the address lines (AD17, AD18, AD19, and AD20) to be sampled "low" by the SHARC processor. It is not enough to just tie these address pins low to ground for host accesses; these lines must be driven low with a strong enough drive strength to overcome the keeper latches present on these pins. If the drive strength provided by the host to the SHARC processor is not strong enough, failure can occur during host accesses resulting in processor core Hang. Using a scope, it can be seen that the HBG (Host Bus Grant) toggles even when the HBR (Host Bus Request) is kept asserted during the failure.
|Chapter: 10||Page: 48|
|DOC ID: DOC-642|
|In the I2S Mode section following the second paragraph (The I2S bus ... transmitted in MSB format.), add the following information bullet:
The I2S bus transmits audio data and control signals over separate lines. The data line carries two multiplexed data channels: the left channel and the right channel. In I2S mode, if both channels on a SPORT are set up to transmit, then SPORT transmit channels (TXxA and TXxB) transmit simultaneously, each transmitting left and right I2S channels. If both channels on a SPORT are set up to receive, the SPORT receive channels (RXxA and RXxB) receive simultaneously, each receiving left and right I2S channels. Data is transmitted in MSB format.
|Chapter: 10||Page: 53|
|DOC ID: DOC-604|
|The information bullet following Figure 10-12 (SPORT Multichannel Mode Pairings: SPORT0 and SPORT2, SPORT1 and SPORT3) requires some editing. Change from:
In multichannel mode, the SCLKx2 and SCLKx3 pin is an input and is internally connected to its corresponding SCLKx0 and SCLKx1 pins. It is not necessary to externally connect SCLKx2 to SCLKx0 and SCLKx1 to SCLKx3.
In multichannel mode, the SCLK2 and SCLK3 pins are inputs and are internally connected to their corresponding SCLK0 and SCLK1 pins. It is not necessary to externally connect SCLK2 to SCLK0 and connect SCLK1 to SCLK3.
|Chapter: 12||Page: 11|
|DOC ID: DOC-594|
|In Table 12-3 (Emulation Control Register (EMUCTL) Definition), the address in the bit 34 (NOBOOT) description is incorrect. Change "0x0080 0004" to "0x0020 0004".|
|Chapter: A||Page: 19|
|DOC ID: DOC-938|
|In table A-5 (STKYx and STKYy Register Bit Descriptions), the description of the AUS bit is not correct. Change from: |
ALU Floating-Point Underflow. A sticky indicator for the ALU AS bit.Change to:
ALU Floating-Point Underflow. A sticky indicator for the ALU AZ bit.