|DOC ID: DOC-1129|
Add the following section to the data sheet.
Timer Clock Timing
Switching Characteristic = tTODP: Timer Output Update Delay After PPI_CLK High = 12
Use the timing diagram from the ADSP-BF534/ADSP-BF536/ADSP-BF537 data
There are also three timing specifications (tTIS, tTIH, and tTOD ) that are missing in Table 39 (Timer Cycle Timing) on page 48. Additionally the unit of measure has changed.
Replace the current table with the following table.
(1) The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
(2) Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
|DOC ID: DOC-1125|
The timing specifications for tDDTTE and tDDTTI are not properly documented in Table 42 of the Data sheet. The two specs are only applicable when the SPORT is in Multichannel mode. Also, when in multichannel mode, SPORT TSCLK is internally connected to RSCLK. Therefore, Page 62, Table 42, should read as follows .
(1) Referenced to drive edge.
(2) Applicable to multichannel mode only.
(3) TSCLKx is tied to RSCLKx.
|DOC ID: DOC-1130|
The minimum specifications for tWL and tWH are incorrectly documented as tSCLK + 1 on page 67 of the data sheet. The minimum for both of these specs is 1 x tSCLK.