Documentation Errata for ADSP-BF531/ADSP-BF532/ADSP-BF533: Blackfin Embedded Processor Data Sheet

The timing specifications for t_DDTTE and t_DDTTI are not properly documented in Table 30 of the Data sheet. The two specs are only applicable when the SPORT is in Multichannel mode. Also, when in multichannel mode, SPORT TSCLK is internally connected to RSCLK. Therefore, Page 37, Table 30, should read as follows.

Note that these parameter values are applicable for all V_DDEXT values

Serial Ports - Enable and Three-State

Parameter		Min	Max	Unit
Switching Characteristics
tDTENE	Data Enable Delay from External TSCLKx1	0		ns
tDDTTE	Data Disable Delay from External TSCLKx1, 2, 3		10	ns
tDTENI	Data Enable Delay from Internal TSCLKx1	-2		ns
tDDTTI	Data Disable Delay from Internal TSCLKx1, 2, 3		3	ns

(1) Referenced to drive edge.

(2) Applicable to multichannel mode only.

(3) TSCLKx is tied to RSCLKx.

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Add the following section to the data sheet.

Timer Clock Timing

Switching Characteristic = t_TODP: Timer Output Update Delay After PPI_CLK High = 12 ns Max

Use the timing diagram from the ADSP-BF534/ADSP-BF536/ADSP-BF537 data sheet.

There are also three timing specifications (t_TIS, t_TIH, and t_TOD ) that are missing in Table 39 (Timer Cycle Timing) on page 48. Additionally the unit of measure has changed.

Replace the current table with the following table.

Timer Cycle Timing

Parameter		VDDEXT = 1.8 V		VDDEXT = 2.5 V/3.3		Unit
		Min	Max	Min	Max
Timing Characteristics
tWL	Timer Pulse Width Input Low1	1 x tSCLK		1 x tSCLK		ns
tWH	Timer Pulse Width Input High1	1 x tSCLK		1 x tSCLK		ns
tTIS	Timer Input Setup Time Before CLKOUT Low2	8.0		6.5		ns
tTIH	Timer Input Hold Time After CLKOUT Low2	1.5		1.5		ns
Switching Characteristics
tHTO	Timer Pulse Width Output	1 x tSCLK	(232 - 1) x tSCLK	1 x tSCLK	(232 - 1) x tSCLK	ns
tTOD	Timer Output Update Delay After CLKOUT High		7.5		6.5	ns

(1) The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.

(2) Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

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