Documentation Errata for ADSP-BF50x Blackfin ® Processor Hardware Reference, Rev. 1.2, February 2013


Chapter:  10 Page: 3
DOC ID: DOC-1421
Change

In the section External Interface, the clock value should be changed from 133 MHz to 100 Mhz as follows:

When clocked internally, the clock source is the processor’s peripheral clock (SCLK). Assuming the peripheral clock is running at 100 MHz, the maximum period for the timer count is ((232-1) / 100 MHz) = 43 seconds.

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Chapter:  13 Page: 8
DOC ID: DOC-1422
Change

In the section Input Noise Filtering (Debouncing), the clock value should be changed from 133 MHz to 100 MHz, and the equations for filter time range should be changed as follows:

Assuming an SCLK frequency of 100 MHz, the filter time range is shown by the following equations:

DPRESCALE = 0b0000
          tfilter = 128*1*10ns = 1.28µs

DPRESCALE = 0b10001
          tfilter = 128*(131072)*10ns = 167772us = (approx.) 168ms

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Chapter:  16 Page: 4
DOC ID: DOC-1423
Change

In the section Serial Clock Signal (SCL), the clock value should be changed from 133 MHz to 83 MHz, and the example should be changed as follows:

Note: It is not always possible to achieve 10 MHz accuracy. In such cases, it is safe to round up the PRESCALE value to the next highest integer. For example, if SCLK is 83 MHz, the PRESCALE value is calculated as 83 MHz/10 MHz = 8.3. In this case, a PRESCALE value of 9 ensures that all timing requirements are met.

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Last Updated: August 20, 2013
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