H.264 Baseline Profile Decoder

The H.264 BP Decoder library is a software component which decodes H.264 Baseline Profile video bit streams and is compliant with ISO/IEC 14496-10:2005(E) of Information technology - Coding of audio- visual objects.

The software has been implemented using C and Blackfin Assembly code. It makes optimal usage of Instruction and Data cache. To optimize video decoding performance, internal SRAMs for Program and Data memory and Memory DMA are also utilized effectively.

H.264 Baseline Profile Decoder

Product Description

The H.264 BP Decoder library is a software component which decodes H.264 Baseline Profile video bit streams and is compliant with ISO/IEC 14496-10:2005(E) of Information technology - Coding of audio- visual objects.

The software has been implemented using C and Blackfin Assembly code. It makes optimal usage of Instruction and Data cache. To optimize video decoding performance, internal SRAMs for Program and Data memory and Memory DMA are also utilized effectively.



Features


Functions


Performance Metrics

MIPS summary:
Code Memory (KiB) Data Memory (MIPS)  
L1 (KiB) L3 (MB) Output Buffer (MB) Average Moving Average Peak Test Case Description
65.7 18.1 3.39 1.03 115 143 QVGA, 384 kbps, 30fps
65.7 18.1 3.39 1.03 251 311 1/2 D1, 768 kbps, 30fps
65.7 18.1 3.39 1.03 515 610 D1, 1500 kbps, 30fps
  • MIPS measured using the bit rates of 384 Kbps, 30 fps for 320x240 (QVGA) size sequence, 768 Kbps, 30 fps for 352x480 (1/2 D1) size sequence and 1.5 Mbps, 30 fps for 720x480 (D1) size sequence, ITU-R BT.656 output, NTSC format, optimal memory layout on ADSP-BF533 Si Rev 0.5 processor.
  • Measurements done with CAS=3 for SDRAM, CCLK=594 MHz, SCLK=118.8 MHz.
  • 32 Kbytes of Data cache and 16Kbytes instruction cache are enabled. The cache is set to "write back" and "large cache" (DCBS=1) mode. Memory DMAs are used.
  • Code memory includes all the code related to the library including 16KB of ICache.
  • "Data RAM for L1" is for one instance, includes Stack, Scratch, Instance/Stage and does not include 32KB of DCache.
  • "Data RAM for L3" is for one instance for a D1 frame including frame buffers for the instance.
  • "Output Buffer" indicates the minimum memory (two PAL frame) required in the settings mentioned above. This is because PAL frame size is bigger than NTSC.
  • 1 MB = 1024 KiB; 1 KiB = 1024 Bytes.
  • NOTE: In deriving the "Moving Average Peak" value, an 8 consecutive frames sliding window was used. An average cycle count was measured for each window of frames, and the worst case average cycle from all the sliding window measurements was determined to be the "Moving Average Peak" value.

Applications


Requirements


Availability and Licensing

Each module supports the Analog Devices, Inc. (ADI) Blackfin Processor family and is a licensed product that is available in object code format. Recipients must sign or accept a license agreement with ADI prior to being shipped or downloading the modules identified in the license agreement.


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