Documentation Errata for ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 Blackfin Embedded Processor Data Sheet

Add the following section to the data sheet.

Timer Clock Timing

Switching Characteristic = t_TODP: Timer Output Update Delay After PPI_CLK High = 12 ns Max

Use the timing diagram from the ADSP-BF534/ADSP-BF536/ADSP-BF537 data sheet.

There are also three timing specifications (t_TIS, t_TIH, and t_TOD ) that are missing in Table 39 (Timer Cycle Timing) on page 48. Additionally the unit of measure has changed.

Replace the current table with the following table.

(1) The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.

(2) Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

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The timing specifications for t_DDTTE and t_DDTTI are not properly documented in Table 42 of the Data sheet. The two specs are only applicable when the SPORT is in Multichannel mode. Also, when in multichannel mode, SPORT TSCLK is internally connected to RSCLK. Therefore, Page 62, Table 42, should read as follows .

(1) Referenced to drive edge.

(2) Applicable to multichannel mode only.

(3) TSCLKx is tied to RSCLKx.

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The minimum specifications for t_WL and t_WH are incorrectly documented as t_SCLK + 1 on page 67 of the data sheet. The minimum for both of these specs is 1 x t_SCLK.

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