Documentation Errata for ADSP-BF534/ADSP-BF536/ADSP-BF537: Blackfin組込み型プロセッサ


Chapter:  Page: 1
DOC ID: DOC-1399
Change
In the features list on Page 1 the description "Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,40-bit shifter is incorrect.
The correct description is "Two 16-bit MACs"

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Chapter:  Page: 39
DOC ID: DOC-1072
Change
In Table 30 a specification is missing.
The following minimum hold-time spec specification should appear in the row immediately after the tSDRE specification:

tHDRE - Receive Data Hold After RSCLKx
The value for this specification is 3.0 ns Minimum

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Chapter:  Page: 41
DOC ID: DOC-1121
Change

The timing specifications for tDDTTE and tDDTTI are not properly documented in Table 32 of the Data sheet. The two specs are only applicable when the SPORT is in Multichannel mode. Also, when in multichannel mode, SPORT TSCLK is internally connected to RSCLK. Therefore, Page 41, Table 32, should read as follows .

Serial Ports - Enable and Three-State
Parameter Min Max Unit
Switching Characteristics
tDTENE Data Enable Delay from External TSCLKx1 0 ns
tDDTTE Data Disable Delay from External TSCLKx1, 2, 3 10 ns
tDTENI Data Enable Delay from Internal TSCLKx1 -2 ns
tDDTTI Data Disable Delay from Internal TSCLKx1, 2, 3 3 ns

(1) Referenced to drive edge.

(2) Applicable to multichannel mode only.

(3) TSCLKx is tied to RSCLKx.

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Last Updated: May 09, 2013
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