|Chapter: 1||Page: 34|
|DOC ID: DOC-550|
|All the host port related timing diagrams in the ADSP-2196 data sheet should be corrected. For accurate HPI timing information, see the ADSP-2191M DSP Microcomputer Data Sheet, Revision A, June 2002.|
|Chapter: N/A||Page: 7|
|DOC ID: DOC-505|
|Figure 2 correctly describes boot memory space with an address range from 0x01 0000 to 0xFe FFFF (16 MWords - 254 pages). The first sentence of the Boot Memory Space section on page 6 (describing boot memory space) doesn't agree with Figure 2. The sentence on page 7 should:|
Boot memory space consists of one off-chip bank with 63 pages.
Boot memory space consists of one off-chip bank of memory as shown in Figure 2. Because the ADSP-2191 has 22 external address lines, the DSP can address the first 63 pages of this space (spanning an address range from 0x01 0000 to 0x40 7FFF). Any access to the full boot memory space (0x01 0000 to 0xFE FFFF, 16M words, 254 pages) asserts the boot memory select (BMS) pin.
|Chapter: N/A||Page: 11|
|DOC ID: DOC-506|
|In the "Host Port Chip Selects" section (second paragraph, third line), the text incorrectly refers to the IJPG register when it should refer to the IOPG register.|
Change the sentence from:
"Before starting a direct access, the Host configures Host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target address page (in the IJPG register)."
Change the sentence to:
"Before starting a direct access, the Host configures Host port interface registers, specifying the width of external data bus (8- or 16-bit) and the target address page (in the IOPG register)."
|Chapter: N/A||Page: 20|
|DOC ID: DOC-508|
|In Table 7, the HACK pin is listed as an output (O), but should be listed as an input/output (I/O). At runtime, HACK is an output only. During reset (and for 10 peripheral cycles after deassertion of reset), HACK is an input. The signal driven on HACK determines the function of the HACK signal (Ready mode or ACK mode).|
|Chapter: N/A||Page: 28|
|DOC ID: DOC-503|
|In Table 11 (External Port Write Cycle Timing), there are two lines for the tDHW parameter. Only the second line (tDHW = tHCLK + 3.4 ns) should refer to footnote 4. |
The first tDHW line (tDHW = 3.4 ns) should NOT refer to footnote 4.
|Chapter: N/A||Page: 33|
|DOC ID: DOC-507|
|In Figure 16 (External Port Bus Request and Grant Cycle Timing), the BR strobe is shown incorrectly. The BR strobe should extend for the duration of the access, and BG should only go high after BR is deasserted by the external device.|
|Chapter: N/A||Page: 36|
|DOC ID: DOC-504|
|In Table 15 (Host Port ACC Mode Write Cycle Timing), the tWAL parameter is incorrectly described.|
Change parameter description from:
"tWAL HWR Asserted to HALE Deasserted (Delay)"
Change parameter description to:
"tWAL HWR Deasserted to HALE Deasserted (Delay)"
|Chapter: N/A||Page: 67|
|DOC ID: DOC-585|
|In the outline dimensions figure, the remove following (or similarly worded) note:
THE ACTUAL POSITION OF EACH BALL IS WITHIN ... mm OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.