ADSP-TS101S MP System Simulation and Analysis
(pdf, 661 kB)
A detailed signal integrity & timing analysis of cluster bus communication for a multiprocessing TigerSHARC system. The system consists of 8 ADSP-TS101S devices, a host processor, and SDRAM with the cluster bus running at 100MHz. Simulation results and physical implementation are included along with discussions of topology, termination, layout, and clock distribution. The report was provided by Plexus, a DSP Collaborative™ 3rd Party member.