Documentation Errata for ADSP-TS201 TigerSHARC Processor Hardware Reference (Revision 1.1, December 2004)

see "Bus Arbitration Protocol" on page 8-38

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Host Bus Grant (HBG) is returned by the TigerSHARC processors when the current master grants bus by asserting HBR.

Host Bus Grant (HBG) is returned by the current TigerSHARC master upon completion of its external access, when an external master has asserted HBR.

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Remove all references to the non-existent BTBMOD bit field.

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In USER mode with the SYS_REG_WE strap pin disabled at reset, the SDRCON register can be written only once after hardware reset and cannot be changed during system operation - subsequent writes to SDRCON are ignored.

To write to the SDRCON register (and SYSCON register) more than once after reset in USER mode, enable the SYS_REG_WE strap pin during reset. In SUPERVISOR mode, SYSCON and SDRCON have no write restrictions.

In SUPERVISOR mode, SDRCON is write once after reset if the SYS_REG_WE strap pin is disabled. If the SYS_REG_WE strap pin is enabled, there are no write restrictions for SDRCON in SUPERVISOR mode. SDRCON can never be written in USER mode regardless of the SYS_REG_WE strap pin setting.

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The BMAX register is set with the maximum number of internal clock cycles (CCLK) for which ...

The BMAX register is set with the maximum number of SOCCLK cycles for which ...

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To keep both of the cycle counter registers coherent between the two write accesses, a shadow register is used to temporarily hold the value written for the CCNT0 register. This temporary value is not written into the actual CCNT0 register until a write has also been issued to the CCNT1 register. So, the CCNT0 and CCNT1 registers must also be written to in the same order as they are read; write to CCNT0 first, then write to CCNT1 to allow for coherent writes of these registers.

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If the timer is active (TMRxRN bit is set), writing a value to the TMRINxH/L register has no effect. Writing a different value to TMRINxH/L while the timer is operating changes the initial value after the next expiration of the timer (when TMRINxH/L value is copied again to the timer).

If the timer is active (TMRxRN bit is set), writing a value to the TMRINxH/L register has an immediate effect. Writing a different value to TMRINxH/L while the timer is operating changes current timer operation, and the value is used as the initial value after the next expiration of the timer (when TMRINxH/L value is copied again to the timer).

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Vector Interrupt

The vector interrupt is a general purpose interrupt. The interrupt is triggered by writing a value to the VIRPT register, or equivalently writing a value to the corresponding location in the interrupt vector table. Unlike typical interrupts, this unique functionality identifies the address of the associated interrupt service routine dynamically at the time the interrupt is triggered. The VIRPT register is accessible to both externally and internally generated write transactions.

Kernel Interrupt

The kernel interrupt is distinct, but functionally identical to the vector interrupt. Like the vector interrupt, the address of the interrupt service routine is defined by the value written to the KERNEL register or the corresponding location in the vector interrupt table. This functionality, in conjunction with the associated priority level of the kernel interrupt (the kernel interrupt is the lowest priority interrupt), makes it well suited for utilization in an RTOS supporting a pre-emptive scheduling paradigm. However, this does not preclude the kernel interrupt from being utilized in other applications. As with the VIRPT register, the KERNEL register is accessible to externally and internally generated write transactions.

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The DMA channel is disabled between DMA sequences in a chain (during chaining).

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In USER mode, SYSCON is write once after reset, unless the SYS_REG_WE strap pin is enabled. In Supervisor mode, SYSCON has no write restrictions.

In SUPERVISOR mode, SYSCON is write once after reset if the SYS_REG_WE strap pin is disabled. If the SYS_REG_WE strap pin is enabled, there are no write restrictions for SYSCON in SUPERVISOR mode. SYSCON can never be written in USER mode regardless of the SYS_REG_WE strap pin setting.

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The SDRAM interface provides a glueless interface with standard SDRAMs—6M bits, 64M bits, 128M bits, 256M bits, and 512M bits. The TigerSHARC processor directly supports a maximum of 64M words x 32 bits of SDRAM per bank for a total of 856M words.

The SDRAM interface provides a glueless interface with standard SDRAMs — 16Mbits, 64Mbits, 128Mbits, 256Mbits, and 512Mbits. The TigerSHARC processor directly supports a maximum of 64M words x 32 bits of SDRAM per bank for a total of 256M words.

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In table 8-13 (Data Throughput Rates), the formulas in the last two rows need to be updated. Change from:

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When LxBCMPI is sampled active, the receiving link port transfers this information to the DMA together with its DMA request. The TCB word counters are cleared by the DMA and the DMA sequence completes.

When LxBCMPI is sampled active, the receiving link port transfers this information to the DMA together with its DMA request. The TCB word counters retain the final number until the next initialization, and the DMA sequence completes.

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