|Chapter: 1||Page: 7|
|DOC ID: DOC-611|
|The external port address bus width is 20 bits(A0-A19)|
|Chapter: 7||Page: 20|
|DOC ID: DOC-541|
|Add the following informational bullet:
Consider a situation where the DSP is doing an external memory read from a FIFO. If an interrupt occurs during a read access to external memory, the read may be aborted. The program control jumps into the interrupt service routine (ISR). In that case, the processor will re-issue the same read after returning from the interrupt. While this is not an issue for static memories, it will cause a loss of synchronization with, for instance, FIFO devices. If operation with a FIFO is required, make sure that the read accesses cannot be interrupted.
|Chapter: 7||Page: 27|
|DOC ID: DOC-612|
|In point # 1, it is mentioned as:
Maximum Core Speed puts the peripheral: core clock ratio at HCLK = 1/2 CCLK and puts the core clock at CCLK= 1600 MHz.
Change to: CCLK= 160 MHz.
|Chapter: 10||Page: 19|
|DOC ID: DOC-546|
|In the code example, DELETE the following lines (lines 2 and 3 on the page): ar = setbit 4 of ar; io(SYSCR)=ar;|
|Chapter: 12||Page: 12|
|DOC ID: DOC-543|
|Replace the following paragraph:
If the—No Boot on Software Reset—Run mode (RMODE) bit of the Next System Configuration Register has been set to 0, following a soft reset, program flow jumps to address 0xFF0000 and begins executing the boot ROM code at that location to reboot the DSP. A software reset can also be used to reset the boot mode without doing an actual reboot. If bit 4 of the Next System Configuration Register has been set to 1, following a soft reset, program flow jumps to address 0x000000 and completes reset without rebooting the DSP.With the following paragraph:
Following a soft reset, program flow jumps to address 0xFF0000 and begins executing the boot ROM code at that location to reboot the DSP.
|Chapter: 12||Page: 35|
|DOC ID: DOC-614|
|Bit 4 of NXTSCR is the RMODE can be set to 0 or 1. Hence it should NOT be shown as RESERVED.|
|Chapter: 13||Page: 3|
|DOC ID: DOC-613|
|For the Peripheral Interrupt Identifier 25, the Interrupt Source and destination is Flag IO Interrupt B|
|Chapter: 21||Page: 32|
|DOC ID: DOC-590|
|It would be useful to add diagram with the register bits definition, reset value and the I/O address for the CANRML register. The new figure for the CANRML register would be ideltical to figure 21-20. Each bit would be defined as RMLn. The reset value for this register would be 0x0000 and the I/O address would be 0x10-0x00E.|
|Chapter: 23||Page: 2|
|DOC ID: DOC-567|
|Replace figure 23-2 in the ADSP-2199x Mixed Signal DSP Controller Hardware Reference with figure B-2 in ADSP-219x/2191 DSP Hardware Reference manual.|
|Chapter: n/a||Page: 2|
|DOC ID: DOC-571|
|In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.|
In the Preface, the IP address of the FTP server is no longer valid. Use ftp://184.108.40.206 instead.
|Chapter: N/A||Page: 38|
|DOC ID: DOC-751|
|Change the bit descriptions for MCDTXPE(bit 2) and MCDRXPE (bit 3) in the SP_MCMC2 register from: |
0 = enabled
0 = disabled