Documentation Errata for ADSP-219x/2191 DSP Hardware Reference (Rev 1.1, August 2003)


Chapter:  9 Page: 6
DOC ID: DOC-624
Change
In Figure 9-1 (SPORT Block Diagram), only one SCLK signal is shown. Actually, each SPORT has two clock signals, a transmit clock signal (TCLK) and a receive clock signal (RCLK).

back to top


Chapter:  9 Page: 13
DOC ID: DOC-535
Change
In the description of the Serial Word Length Select (SLEN) bit field, SLEN is referred to as "the SLEN bit" a number of times. This reference should change to "the SLEN bits" where it appears on page 9-13 and 9-16.

back to top


Chapter:  9 Page: 18
DOC ID: DOC-515
Change
The last paragraph on the page needs an additional sentence.

Change from:

An interrupt is generated when the SPx_RX buffer has been loaded with a received word (the SPx_RX buffer is "not empty"). This interrupt is masked out if SPORT DMA is enabled.

Change to:

An interrupt is generated when the SPx_RX buffer has been loaded with a received word (the SPx_RX buffer is "not empty"). This interrupt will continue to be generated as long as the SPx_RX buffer is "not empty". This interrupt is masked out if SPORT DMA is enabled.

back to top


Chapter:  14 Page: 47
DOC ID: DOC-499
Change
Because flags only can be edge- or level-sensitive, eliminate the following sentence (last sentence on page):
If the flag pin is configured for edge-sensitivity, the FSSR register also specifies the flag pin's sensitivity for rising edge, falling edge, or both edges.

back to top


Chapter:  23 Page: 72
DOC ID: DOC-659
Change
The description of memory bank width selection is confusing on this page. Delete the sentence:
Each of these banks can also be configured to support either 8-bit wide memories or 16-bit wide memories on a bank basis.

back to top


Chapter: B Page: 15
DOC ID: DOC-545
Change
In Table B-1 (I/O Processor Registers Memory Map), delete the entries for the FSPRC and FSPRS registers. There is only an FSPR register at address 0x06:0x008. Also in Table B-1, delete the entries for the FSBERC and FSBERS registers. There is only an FSBER register at address 0x06:0x00C.

back to top


Chapter: B Page: 45
DOC ID: DOC-548
Change
The default value of the SPORT status register is mentioned incorrectly as 0x0000.

The default value of the SPORT status register is actually 0x0004.

back to top


Chapter: B Page: 103
DOC ID: DOC-657
Change
The description of memory bank width selection is confusing on this page. Delete the sentence:
Each of these banks can also be configured to support 8-bit-wide or 16-bit-wide memories on a bank basis.

back to top


Chapter: n/a Page: 6
DOC ID: DOC-570
Change
In the Preface, the European Fax number is incorrect. Use +49-89-76903-157 instead.

In the Preface, the IP address of the FTP server is no longer valid. Use ftp://137.71.25.69 instead.

back to top


Last Updated: June 07, 2007
沪ICP备09046653号
Send Feedback X
content here.
content here.

Send Feedback

Close