ANALOG DEVICES INTRODUCES INDUSTRY’S LOWEST POWER QUAD-CHANNEL, JITTER ATTENUATING, CLOCK TRANSLATOR

New clock reduces cost of ownership for OTN mapping and Ethernet line cards in optical and networking communications applications.

Norwood, MA (05/20/2014) - Analog Devices, Inc. (NASDAQ: ADI) introduced today the AD9554 multi-service adaptive quad-channel clock translator with clock multiplier, which provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). Its embedded cross-point switch at the input means greater flexibility and lower cost of ownership than maintaining different clocking configurations of non-flexible parts. The AD9554 dissipates only 940 mW of power while generating up to eight output clocks over an output range of 430 kHz to 941 MHz, synchronized to four 2-kHz to 1-GHz external input references, with a loop bandwidth as low as 0.1 Hz. The four analog-digital phase-locked loops (ADPLL) enable the reduction of input jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed. The AD9554 has adaptive clocking capability that allows the user to dynamically change the DPLL divide ratios while they are locked.

Analog Devices Introduces Industry’s Lowest Power Quad-Channel

  • Download AD9554 data sheet, order samples and evaluation boards
  • Connect with engineers and ADI product experts on EngineerZone™, an online technical support community

The AD9554 clock’s high level of integration, adaptive clocking capability, and OTN mapping algorithm embedded in DPLL, can reduce system costs by simplifying clocking circuitry and eliminating software control routines. Output jitter is 250 fs over the 50-kHz to 80–MHz range and 350 fs over the 12-kHz to 20-MHz range.

AD9554 Key Features

  • GR-1244 Stratum 3 stability in holdover mode
  • Smooth reference switchover with virtually no disturbance on output phase
  • Adaptive clocking allows dynamic adjustment of feedback dividers in OTN mapping/demapping
  • Quad ADPLL architecture:
    - Four reference inputs (single-ended or differential)
    - Eight outputs (single-ended or differential)
  • 4x4 crosspoint allows any reference input to drive any output
  • Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261, and ITU-T G.8262
  • Loop bandwidth as low as 0.1Hz to guarantee SyncE compliance

Pricing, Availability and Complementary Components

Product Sample Availability Full Production Price Each Per 1K Packaging
AD9554BCPZ NOW NOW $21.33 72-lead LFCSP

The AD9554 can be designed into networking applications with ADI’s:
AD9525 low-jitter clock generator
ADF4150 fractional-N PLL synthesizer
ADF4350 wideband synthesizer with integrated VCO

About Analog Devices

Innovation, performance, and excellence are the cultural pillars on which Analog Devices has built one of the longest standing, highest growth companies within the technology sector. Acknowledged industry-wide as the world leader in data conversion and signal conditioning technology, Analog Devices serves over 60,000 customers, representing virtually all types of electronic equipment. Analog Devices is headquartered in Norwood, Massachusetts, with design and manufacturing facilities throughout the world. Analog Devices is included in the S&P 500 Index.

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Editor's Contact Information:

Jim Surber
336-605-4365

jim.surber@analog.com

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