The ADM1186-1 and ADM1186-2 are integrated, four-channel, voltage monitoring and sequencing devices. A 2.7 V to 5.5 V power supply is required on the VCC pin for power. Four precision comparators monitor four voltage rails, with all comparators sharing a 0.6 V reference and a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the Under Voltage (UV) trip points for the monitored supply rails. The ADM1186-1 and ADM1186-2 have four open drain enable outputs, OUTx, that are used to enable power supplies. An open drain power good output, PWRGD, is provided that indicates the four VINx inputs are above their UV thresholds. A state machine monitors the state of the UP and DOWN pins on the ADM1186-1 or the UP/overbar: DOWN pin on the ADM1186-2 to control the supply sequencing direction. In the ‘Wait Start’ state, a rising edge transition on the UP or UP/DOWN pin triggers a power-up sequence. A falling edge transition on the DOWN or UP/DOWN pin in the ‘Power Up Done’ state triggers a power down sequence. During a power up sequence, the state machine enables each power supply in turn. The supply output voltage is monitored to determine if it rises above the UV threshold level within a user defined duration called the blanking time. If a supply rises above the UV threshold then the next enable output in the sequence is turned on. In addition to the blanking time a user may also define sequencing time delays between each enable output turning on. When all four enable outputs are on, and the four VINx pins are above their UV trip points the power up sequence is complete. The ADM1186-1 provides an open drain pin, SEQ_DONE, that is asserted high to provide an indication that an up sequence is complete. The SEQ_DONE pins is allows multiple cascaded ADM1186-1 devices to be perform controlled power up and down sequences. During a power down sequence the enable outputs turn off in reverse order. The sequence time delays between successive supplies the same as during the power up sequence, and no blanking time is used during a power down sequence. At the end of a down sequence the SEQ_DONE pin is brought low. During sequencing and when powered up, the state machine continuously monitors for any fault conditions. Faults include a UV condition on any of the inputs, or an unexpected control input. Any fault that occurs causes the state machine to enter a fault handler. This immediately turns off all enable outputs, and ensures that the device is ready to start a new up sequence. The ADM1186-1 has a bi-directional open drain pin, FAULT, that facilitates fault handling when using multiple devices. An ADM1186-1 experiencing a fault condition drives the FAULT pin low, causing other connected ADM1186-1devices to enter their own fault handling state.. The ADM1186-1 is available in a 20-lead QSOP package and the ADM1186-2 is available in a 16-lead QSOP package.
|Title||Content Type||File Type|
|ADM1186: Quad Voltage Up and Down Sequencer and Monitor with Programmable Timing Data Sheet (Rev B, 04/2013) (pdf, 406 kB)||Data Sheets|
|Supervisory Devices Complementary Parts Guide for Altera FPGAs (pdf, 664 kB)||Product Selection Guide|
|Supervisory Devices Complementary Parts Guide for Xilinx FPGAs (pdf, 661 kB)||Product Selection Guide|
|Supervisory Devices Complementary Parts Guide for Altera FPGAs (pdf, 664 kB)||Solutions Bulletins|
|Supervisory Devices Complementary Parts Guide for Xilinx FPGAs (pdf, 661 kB)||Solutions Bulletins|
|Voltage Monitoring and Sequencing (2009/2010) (pdf)||Overview|
|What can 40 years of analog leadership do for your power management design?||Overview||HTML|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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