MIPS summary:
| Code Memory (KiB) |
Data RAM (MB) |
Output Buffer (MB) |
Cycles/pel (MIPS) |
| L1(KiB) |
L3 (MB) |
Average |
Moving Average Peak |
| 43.83 |
35.80 |
1.78 |
2.06 |
38 (390) |
43 (446) |
- MIPS measured using a bit rate of 6 Mbps, 30 fps, 720x480 (D1) image size, ITU-R BT.656 output, NTSC format, optimal memory layout on ADSP-BF533 rev 0.5 processor.
- Measurements done with CAS=3 for SDRAM, CCLK=594 MHz, SCLK=118.8 MHz.
- 32 Kbytes of data cache and 16Kbytes instruction cache are enabled. The cache is set in "write back" and "large cache" (DCBS=1) mode. Memory DMAs are used.
- Code memory includes all the codes related to the library including 16KB of ICache.
- "Data RAM for L1" is for one instance, includes Stack, Scratch, Instance/Stage and does not include 32KB of DCache.
- "Data RAM for L3" is for one instance for a D1 frame including frame buffers for the instance.
- "Output Buffer" indicates the minimum memory (two PAL frame) required in the settings mentioned above. This is because PAL frame size is bigger than NTSC.
- 1 MB = 1024 KiB; 1 KiB = 1024 Bytes.
NOTE: In deriving the "Moving Average Peak" value, an 8 consecutive frames sliding window was used. An average cycle count was measured for each window of frames, and the worst case average cycle from all the sliding window measurements was determined to be the "Moving Average Peak" value.
