Documentation Errata for ADSP-BF531/ADSP-BF532/ADSP-BF533: Blackfin Embedded Processor Data Sheet
| Chapter: N/A | Page: 3 |
| Reference Number: 36893 | |
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The description of voltage regulator in General Description section include specifications for input voltage supply (specific voltage range). These specific voltage references should change to a reference to the external I/O voltage supply. The revision suggestion is to change from: The voltage regulator provides a range of core voltage levels from a single 2.25 V to 3.6 V input. Change to: The voltage regulator provides a range of core voltage levels when supplied from VDDEXT. | |
| Chapter: N/A | Page: 18 |
| Reference Number: 26706 | |
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| Change this: "All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins, which are driven high. If BR is active, then the memory pins are also three-stated. All unused I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs as noted in the table footnotes." To this: "All pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins. These pins are all driven high, with the exception of CLKOUT, which toggles at the system clock rate. If, however, BR is active, then the memory pins are also three-stated. All unused I/O pins have their input buffers disabled with the exception of the pins that need pull-ups or pull-downs as noted in the table footnotes." | |
| Chapter: N/A | Page: 21 |
| Reference Number: 34037 | |
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In the Operating Conditions table, a footnote needs to be added to the VDDEXT External Supply Voltage parameter (row 5). Add the footnote:
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| Chapter: N/A | Page: 22 |
| Reference Number: 35033 | |
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| In the Electrical Characteristics table, all of the Idd specifications beneath the separator (Idddeepsleep, Iddsleep, and the 5 Idd_typ) are incorrectly located in the "Typical" column. These are guaranteed maximum secifications for the test conditions described and should appear in the Max column. | |
| Chapter: N/A | Page: 22 |
| Reference Number: 35223 | |
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In the Electrical Characteristics table, change the description of the IDDHIBERNATE parameter from: VDDINT Current in Hibernate State Change to: from: VDDEXT Current in Hibernate State | |
| Chapter: N/A | Page: 22 |
| Reference Number: 36884 | |
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| The Test Conditions column entry for IDDHIBERNATE in the Electrical Characteristics table is missing the condition "CLKIN = 0 MHz". Add this condition to the entry. | |
| Chapter: N/A | Page: 23 |
| Reference Number: 34806 | |
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The Absolute Maximum Ratings table must provide a specification for Input Voltage tolerance when VDDEXT is not with Operating Specifications. To address this, a footnote should be added to the Input Voltage parameter in row 3 of the table. Add the new footnote 2:
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| Chapter: N/A | Page: 28 |
| Reference Number: 34069 | |
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In table 19 (SDRAM Interface Timing), change footnote 1 from:
Change to:
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| Chapter: N/A | Page: 35 |
| Reference Number: 36318 | |
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In table 25 (External Late Frame Sync), the table refers to the multi-channel enable bit as MCE (incorrect) rather that MCMEN (correct). Change the following:
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| Chapter: N/A | Page: 55 |
| Reference Number: 29216 | |
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| In Table 38 (176-Lead LQFP Pin Assignment, Alphabetically by Signal), the signal name for DATA2 is omitted.
Change the first instance of the signal name DATA10 (occuring directly after DATA1) to DATA2 and change the Lead No. from 103 to 114. (This information is correct in Table 41, 176-Lead LQFP Pin Assignment, Numerically by Lead Number.) | |
Last Updated: August 27, 2008