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| Chapter: 3 |
Page: 13 |
| Reference Number: 33846 |
| Change |
In table 3-6 (Resets), the Source entry for the core double-fault reset row is incorrect. Change the Source text from:If the core enters a double-fault state, a reset can be caused by unmasking the core double fault reset mask bit in the system interrupt controller interrupt mask register (SIC_IMASK).
Change the Source text to:If the core enters a double-fault state, and the Core Double Fault Reset Enable bit (DOUBLE_FAULT) is set in the SWRST register, then a software reset will occur. |
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| Chapter: 8 |
Page: 28 |
| Reference Number: 39553 |
| Change |
In figure 8-8 (Voltage Regulator Control Register), change the description of the WAKE bit to:
WAKE (RTC Wakeup Enable)
0 - RTC wakeups disabled
1 - RTC wakeups enabled |
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| Chapter: 8 |
Page: 28 |
| Reference Number: 39555 |
| Change |
Replace the sentence before the first bullet, the first two bullets of the list, and the WAKE bullet to the following ((the rest of the bullets, starting with "External GP event", are okay as-is):
The internal supply regulator can be woken up by several user-selectable events, all of which are controlled in the VR_CTL register:
- Assertion of the
RESET pin will always exit hibernate state and requires no modification to the VR_CTL register. - RTC event. Set the wakeup-enable (
WAKE) control bit to enable wakeup upon a RTC interrupt. This can be any of the RTC interrupts (alarm, daily alarm, day, hour, minute, second, or stopwatch). - WAKE -- The wakeup-enable (
WAKE) control bit allows the voltage regulator to be awakened from Hibernate (FREQ = b#00) upon an interrupt from the RTC.
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| Chapter: 9 |
Page: 53 |
| Reference Number: 39586 |
| Change |
Delete the text: For example, the current DMA address (DMAx_CURR_ADDR) crossed the 0xF000 0000 boundary, or the current descriptor pointer (DMAx_CURR_DESC_PTR) crossed the 0xF000 0000 boundary. |
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| Chapter: 10 |
Page: 6 |
| Reference Number: 39578 |
| Change |
In figure 10-2 (ADSP-BF539 as Slave SPI Device), in the box on the right, change the label SCLK0 to SCK0. |
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| Chapter: 16 |
Page: 45 |
| Reference Number: 40014 |
| Change |
Add the following information bullet in the TCNTL Register section: Note: The TINT bit in the TCNTL register indicates that an interrupt has been generated. Note that this is not a W1C bit. Write a 0 to clear it. However, the write is optional. It is not required to clear interrupt requests. The core time module doesn’t provide any further interrupt enable bit. When the timer is enabled, interrupts can be masked in the CEC controller.
Also, in figure 16-26 (Core Timer Control Register) on page 16-47, the bit TINT bit description must change from: TINT - W1C
Change to: TINT - W0C |
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| Chapter: 16 |
Page: 49 |
| Reference Number: 39582 |
| Change |
Where it appears, change WDG_CTL to WDOG_CTL. |
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| Chapter: 19 |
Page: 16 |
| Reference Number: 35197 |
| Change |
In the second paragraph on the page, the first sentence about signal edge needs to be worded more specifically. Change from: If the CAN module detects a signal edge outside the synchronization segment, it can automatically move the sampling point by one or more TQs.
Change to: If the CAN module detects a recessive-to-dominant edge outside the synchronization segment, it can automatically move the sampling point such that the CAN bit is still handled properly. |
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