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| Chapter: 6 |
Page: 3 |
| Reference Number: 34294 |
| Change |
In figure 6-1 (External Memory Map), the word "by" is missing. The note should corrected as follows (missing word in bold text):NOTE: RESERVED OFF-CHIP MEMORY AREAS ARE LABELED IN THE DIAGRAM ABOVE. ALL OTHER OFF-CHIP SYSTEM RESOURCES ARE ADDRESSABLE BY BOTH THE CORE AND THE SYSTEM. |
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| Chapter: 6 |
Page: 38 |
| Reference Number: 39618 |
| Change |
In the tRC, tRFC, and tXSR timing specification definitions, change from:
SDC setting: tRAS + tRP normalized system clock cycles
Change to: SDC setting: User must ensure that tRP + tRAS >= max(tRC,tRFC,tXSR)
Also, add the following information bullet to this section: In typical applications making sequential (not random) accesses to the SDRAM memory, the tRAS timing parameter is less critical than tRP. System designers should be aware that whenever the (tRP + tRAS) in their design is violating one of the other timing specifications, then they should increase the tRAS parameter. |
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| Chapter: 8 |
Page: 23 |
| Reference Number: 39376 |
| Change |
Remove all mention of slew rate control registers (including PORTF_SLEW, PORTG_SLEW, PORTH_SLEW, and NONGPIO_SLEW) and slew control features. Slew rate control is NOT a supported feature, and usage of this feature MAY DAMAGE the processor. Affected pages include: 8-23, 8-25, 8-26, 17-15, 17-16, A-9, and 1-9. In PDF of book, search on "slew". |
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| Chapter: 15 |
Page: 19 |
| Reference Number: 39768 |
| Change |
| Remove references to the HWAIT alternate pin (HWAITA, OTP_ALTERNATE_HWAIT, dHWAIT). This pin does not exist on the ADSP-BF52x processors. |
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| Chapter: 15 |
Page: 61 |
| Reference Number: 35631 |
| Change |
In the "Flash Boot Modes" section, change from (bold text): These booting modes are intended to boot from flash or EEPROM memories or even from battery-buffered SRAMs. The flash boot modes are activated by BMODE = 0000. Although this is a single BMODE setting, the ADSP-BF52x products support various configurations.
Change to (bold text): These booting modes are intended to boot from flash or EEPROM memories or even from battery-buffered SRAMs. The flash boot modes are activated by BMODE = 0001. Although this is a single BMODE setting, the ADSP-BF52x products support various configurations.
This same error appears on page (15-60). Change from (bold text): The no-boot mode is not the same as the bypass mode featured by the ADSP-BF53x processor. To simulate that bypass mode feature using BMODE = 0000, see "Direct Code Execution" on page15-35 and "Direct Code Execution" on page15-117.
Change to (bold text): The no-boot mode is not the same as the bypass mode featured by the ADSP-BF53x processor. To simulate that bypass mode feature using BMODE = 0001, see "Direct Code Execution" on page15-35 and "Direct Code Execution" on page15-117. |
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| Chapter: 15 |
Page: 111 |
| Reference Number: 36276 |
| Change |
The code in listing 15-1 (Core and System Reset) is insufficient for performing a soft system and core reset. Add the following text immediately after the reference to listing 15-1 in the "Core and System Reset" section: As described in the code comments below, the system soft reset takes 5 system clock cycles to complete, so a delay loop is needed. This code must reside in L1 memory for the system soft reset to work properly.
Also, replace listing 15-1 with the following code: /* Issue system soft reset */
P0.L = LO(SWRST) ;
P0.H = HI(SWRST) ;
R0.L = 0x0007 ;
W[P0] = R0 ;
SSYNC ;
/* **********
Wait for System reset to complete (needs to be 5 SCLKs). Assuming a worst case CCLK:SCLK ratio (15:1), use 5*15 = 75 as the loop count.
********** */
P1 = 75;
LSETUP(start, end) LCO = P1 ;
start:
end:
NOP ;
/* Clear system soft reset */
R0.L = 0x0000 ;
W[P0] = R0 ;
SSYNC ;
/* Core reset - forces reboot */
RAISE 1 ;
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| Chapter: 17 |
Page: 763 |
| Reference Number: 39388 |
| Change |
The TWI_DT settings in the NONGPIO_DRIVE register description are NOT correct. The correct settings are: | TWI_DT | Nominal Vddext | Nominal Vbustwi for TWI pins SCL and SDA |
|---|
| 000: | 3.3V Vddext | 3.3V Vbustwi | | 001: | 1.8 V Vddext | 1.8V Vbustwi | | 010: | 2.5 V Vddext | 3.3V Vbustwi | | 011: | 1.8V Vddext | 3.3V Vbustwi | | 100: | 3.3V Vddext | 5 V Vbustwi | | 101: | 1.8V Vddext | 2.5V Vbustwi | | 110: | 2.5 V Vddext | 2.5V Vbustwi | | 110: | Reserved | |
Note that Table 11 in the PrE data sheet also has the correct settings. |
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