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| Chapter: 6 |
Page: 29 |
| Reference Number: 40376 |
| Change |
In Figure 6-11, attach the following description to bit #5, which is described as reserved.
MDDRENABLE (Mobile DDR Enable)
R/W
Enables Mobile DDR functionality (See Figure 6-7, “Memory Control Register 3 (in Mobile DDR mode)” on page 6-25.) |
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| Chapter: 6 |
Page: 78 |
| Reference Number: 36470 |
| Change |
| In Figure 6-17, ARE should have been shown to be asserted after Setup number of cycles. |
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| Chapter: 9 |
Page: 32 |
| Reference Number: 40096 |
| Change |
In Table 9-13 swap the PORTG and PORTG_DIR_CLEAR labels in column "Register Name."
PORTG is at address FFC01584 and PORTG_DIR_CLEAR is at FFC01594.
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| Chapter: 15 |
Page: 34 |
| Reference Number: 39868 |
| Change |
In table 15-5 (Header for a Single Block Boot Stream) there are multiple errors in the first row of the table. (See change from/to below.) CHANGE FROM in Row 1 of
Table 15-5. Header for a Single Block Boot Stream | Field | Value | Comments | BLOCK CODE
(DMACODE & 0x1) | 0xAD32 0001 | 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | | CHANGE TO in Row 1 of
Table 15-5. Header for a Single Block Boot Stream | Field | Value | Comments | | BLOCK CODE | 0xAD33 C001 | 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | (DMACODE & 0x1) | |
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| Chapter: 17 |
Page: 36 |
| Reference Number: 39794 |
| Change |
In table 17-6 (Header for a Single Block Boot Stream) there are multiple errors in the first row of the table. (See change from/to below.) CHANGE FROM in Row 1 of
Table 17-6. Header for a Single Block Boot Stream | Field | Value | Comments | BLOCK CODE
(DMACODE & 0x1) | 0xAD32 0001 | 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | | CHANGE TO in Row 1 of
Table 17-6. Header for a Single Block Boot Stream | Field | Value | Comments | | BLOCK CODE | 0xAD33 C001 | 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | (DMACODE & 0x1) | |
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| Chapter: 17 |
Page: 154 |
| Reference Number: 40097 |
| Change |
The following sentence needs update. {Note that also the cross references are off.} Change from: To perform a system and core reset, use the code shown in Listing 17-2 or Listing 17-3.
Change to: To perform a system reset, use the code shown in Listing 17-1 or Listing 17-2. |
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