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| Chapter: 4 |
Page: 24 |
| Reference Number: 40248 |
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In the section "Hardware Loops," append the following text (before 'Two-Dimensional Loops'):
If the processor transitions from User mode to Supervisor mode, the LSB of the LBx registers will be set by the hardware. Similarly, if it transitions from Supervisor mode to User mode, this bit will be get cleared automatically. |
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| Chapter: 4 |
Page: 41 |
| Reference Number: 40260 |
| Change |
To the ILATCH Register description, add the following Note:
For an interrupt which is already being serviced, the ILATCH bit of the corresponding IVG will not be set, if the interrupt is re-triggered at the system source level. However, the corresponding bit in the SIC_ISR register will remain set. Even if the ILATCH bit for the particular IVG is not set, no interrupts are lost in this process; the System Interrupt Controller would have acknowleded this info internally to the Core Event Controller. |
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| Chapter: 4 |
Page: 48 |
| Reference Number: 40253 |
| Change |
The last paragraph on the page describing the NMI input pin should include this information:
The NMI pin is level-sensitive and should always be pulled to its deasserted state if unused. On some derivatives, the NMI input is active high and on some it is active low. Please refer to the specific data sheet for your processor. |
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| Chapter: 4 |
Page: 55 |
| Reference Number: 40247 |
| Change |
In the section "Self-Nesting of Core Interrupts 4-55," append the following text:
When self-nesting is enabled, the processor sets the last bit of the RETI register and when it pops it, it checks for this bit and if it's set then it does not clear the IPEND register. Thus the corresponding IPEND bit is not cleared on execution of RTI and no interrupts are lost in this process. Note that it is the responsibility of the user to correctly push and pop the RETI register values, to/from the Stack. |
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| Chapter: 10 |
Page: 11 |
| Reference Number: 40043 |
| Change |
Remove the following false statement:
The Pop instruction cannot be issued in parallel with other instructions. |
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| Chapter: 17 |
Page: 3 |
| Reference Number: 39869 |
| Change |
In the Functional Description section, change from: This instruction does not cause address exception violations. If a protection violation associated with the address occurs, the instruction acts as a NOP and does not cause a protection violation exception.
Change this text into the following paragraph (applying to all processors, except the ADSP-BF535) and an information note (which applies to just the ADSP-BF535): This instruction may generate CPLB exceptions (see Table 4-11 for details). For example, exception 0x26 can be generated upon execution of the PREFETCH[P0] instruction if P0 points to an invalid memory location. However, external memory will not be accessed when any of these exceptions are generated. - For ADSP-BF535 processors only, this instruction does not cause address exception violations. If a protection violation associated with the address occurs, the instruction acts as a NOP and does not cause a protection violation exception.
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