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Documentation Errata for ADSP-BF561 Blackfin Processor Hardware Reference (Revision 1.1, February 2007)


Chapter:  3 Page: 13
Reference Number: 33847
Change
In table 3-6 (Resets), the Source entry for the core double-fault reset row is incorrect. Change the Source text from:
If the core enters a double-fault state, a reset can be caused by unmasking the core double fault reset mask bit in the system interrupt controller interrupt mask register (SIC_IMASK).

Change the Source text to:
If the core enters a double-fault state, and the Core Double Fault Reset Enable bit (DOUBLE_FAULT) is set in the SWRST register, then a software reset will occur.

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Chapter:  3 Page: 14
Reference Number: 36183
Change
As currently written, the "System Reset Configuration Register B (SICB_SYSCR)" section describes the register as though it is only used as an interrupt, when in actuality the register serves as a means of communication between the cores that can also generate interrupts.

Change from:
System Reset Configuration Register B (SICB_SYSCR)

In the ADSP-BF561 there is a provision for either core to interrupt itself or the other core. The SICB_SYSCR register Bits[13:6] are used for this purpose. Figure 3-3 on page 3-16 describes this register. Bits[9:6] are written "1" to set the proper interrupt, and Bits[13:10] are written "1" to clear the interrupt.

Core A can write "1" to Bit 6 of SICB_SYSCR to interrupt itself or to Bit 7 to interrupt Core B. Similarly, Core B can write "1" to Bit 8 of SICB_SYSCR to interrupt Core A or to Bit 9 to interrupt itself. Writing "1" to Bits 10, 11, 12, 13, respectively, would clear these interrupts.

This enables either core to interrupt one or both cores at the same time.


Change to:
System Reset Configuration Register B (SICB_SYSCR)

The SICB_SYSCR register provides the ability for one core to signal the other core via supplemental interrupts. Either core can raise either of the supplemental interrupts on itself or on the other core. The SICB_SYSCR register bits[13:6] are used for this purpose. Figure 3-3 on page 3-16 describes this register. Software should write a "1" to bits[9:6] to set the associated supplemental interrupt. Once set, these bits become sticky until the supplemental interrupt is cleared when software writes a "1" to the corresponding bit in bits[13:10].

For example, Core A can write a "1" bit 7 of SICB_SYSCR to interrupt Core B. Core B would then need to write a "1" to bit 11 to clear the interrupt. Similarly, Core B can write a "1" to bit 8 of SICB_SYSCR to interrupt Core A. Core A would then need to write a "1" to bit 12 to clear the interrupt.

This enables either core to interrupt one or both cores at the same time. To enable an interrupt vector as a result of a supplemental interrupt, the supplemental interrupt being used must be enabled in the appropriate SIC_IMASKx register (see System Interrupt Mask Registers (SIC_IMASKx) on page 4-31).

If no interrupt is desired, or if handshaking between the cores is needed for core synchronization reasons, the SICB_SYSCR register can also be used for polling. Since the supplemental interrupt bits[9:6] become sticky once set, reads of this register will always return the status of the supplemental interrupt requests in bits[9:6]. For example, if Core A needs to know when the supplemental interrupt it raises on Core B has been serviced, it can immediately poll the bit it just set and wait for it to clear, provided Core B writes a "1" to the associated clear bit.

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Chapter:  3 Page: 18
Reference Number: 36280
Change
The code in listing 3-4 (Core and System Reset) is insufficient for performing a soft system and core reset. Add the following text immediately after the reference to listing 3-4 in the "Core and System Reset" section:
As described in the code comments below, the system soft reset takes 5 system clock cycles to complete, so a delay loop is needed. This code must reside in L1 memory for the system soft reset to work properly.

Also, replace listing 3-4 with the following code:

/* Issue system soft reset */
P0.L = LO(SICA_SWRST) ;
P0.H = HI(SICA_SWRST) ;
R0.L = 0x0007 ;
W[P0] = R0 ;
SSYNC ;

/* **********
Wait for System reset to complete (needs to be 5 SCLKs). Assuming a worst case CCLK:SCLK ratio (15:1), use 5*15 = 75 as the loop count.
********** */
P1 = 75;
LSETUP(start, end) LCO = P1 ;
   start:
   end:
      NOP ;

/* Clear system soft reset */
R0.L = 0x0000 ;
W[P0] = R0 ;
SSYNC ;

/* Core reset - forces reboot */
RAISE 1 ;

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Chapter:  8 Page: 8
Reference Number: 36325
Change
In figure 8-3 (The PLL Control Register), bit 4 of PLL_CTL is the ALT_TIMING bit. The figure should be revised such that this bit should be unshaded and keep the reset value of 0. Add the following bit definition to the figure:
ALT_TIMING (Alternate Timing)
0 - Data/Frame Sync sampled on opposite PPI_CLK edges
1 - Data/Frame Sync sampled on same PPI_CLK edge
(For more information, see Chapter 11, "Parallel Peripheral Interface".

Also, added an information bullet on page 11-1 in the 2nd paragraph (immediately after the sentence "It has a dedicated clock pin, three frame sync pins, and eight dedicated data pins") as follows:
The default behavior is for frame syncs and data to be sampled on opposite PPI clock edges. To change this behavior such that frame sync and data are sampled on the same PPI clock edge, set the ALT_TIMING bit in the PLL_CTL register. For more information about PPI controls, see Figure 11-1 on page 11-4.

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Chapter:  8 Page: 8
Reference Number: 36735
Change
In figure 8-3 (The PLL Control Register), changes are needed to document bit 15 (SPORT_HYS). Bit 15 should be unshaded in the diagram and keep the reset value of 0. The following bit definition should added:
SPORT_HYS (SPORT Hysteresis)
0 - No added hysteresis to SPORT input pins
1 - Add 250 mV of hysteresis to SPORT input pins

In the text following the figure, add the following as a bullet before MSEL[5:0]:
SPORT_HYS - This bit is used to add 250 mV of hysteresis to the SPORT input pins to provide better immunity to system noise on SPORT clock and frame sync signals configured as inputs.

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Chapter:  8 Page: 8
Reference Number: 36737
Change
In figure 8-3 (The PLL Control Register), the following changes are needed:
  • "Output Delay" (bit 7) should be named "OUT_DELAY"
  • "Input Delay" (bit 6) should be named "IN_DELAY"

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Chapter:  8 Page: 26
Reference Number: 31257
Change

In the VR_CTL register, the name of bit 15 is SCKELOW, not CKELOW.

This correction is needed on:

  • Page 8-26 (three instances)
  • Page 8-30 (on instance)
  • Page 16-43 (one instance)
  • Page I-4 (one instance)

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Chapter:  8 Page: 28
Reference Number: 31254
Change

In table 8-7 (VLEV Encodings), the following rows should change:

Changes to VLEV Encodings Table
VLEV Voltage
1110 1.25 volts
1111 1.30 volts


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Chapter:  9 Page: 24
Reference Number: 35051
Change
The PMAP field enumeration is off by 1 in Figure 9-13. The definitions should go from 0x0 - 0x6 instead of 0x1 - 0x7, as follows:
0x0 - SPORT0 RX
0x1 - SPORT0 TX
0x2 - SPORT1 RX
0x3 - SPORT1 TX
0x4 - SPI
0x5 - UART RX
0x6 - UART TX

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Chapter:  9 Page: 65
Reference Number: 39587
Change
Delete the text:
For example, the current DMA address (DMAx_CURR_ADDR) crossed the 0xF000 0000 boundary, or the current descriptor pointer (DMAx_CURR_DESC_PTR) crossed the 0xF000 0000 boundary.

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Chapter:  10 Page: 4
Reference Number: 35141
Change
There are references to active and inactive edges throughout the chapter, which are inaccurate and insufficient to cover the possible modes of operation for the SPI peripheral. The following changes are needed:
  • On page 10-4, in the 3rd paragraph under the "Serial Peripheral Interface Clock Signal (SCK)" section: Remove the 2nd sentence that reads "The data is always shifted out on active edges of the clock and sampled on inactive edges of the clock." and append a parenthetical reference at the end of the paragraph that says "(see "SPI Transfer Protocols" on page 10-20).".


  • On page 10-20:
    • In the 1st paragraph under the "SPI Transfer Protocols" section: insert parenthetical text at the end of the 1st sentence after "serial clock phase and polarity" that reads "(SPI modes 0-3)".


    • At the end of the second sentence that ends "using the CPOL and CPHA bits in SPI_CTL", add the following text: ", as shown in Figure 10-11".


    • Insert new diagram showing clock polarity (CPOL) versus clock phase (CPHA) for modes 0, 1, 2, and 3. Diagram goes immediately after the new text of regarding "Figure 10-11". Title the diagram "Figure 10-11. SPI Modes of Operation".


    • Re-enumerate all subsequent figures in the chapter.


  • On page 10-23:
    • In the 2nd paragraph under the "Clock Signals" section: Delete the parenthetical references to "(the active edge)" and "(the sampling edge)".


    • Add parenthetical reference at the end of the paragraph to the new Figure 10-11 inserted on page 10-20.


  • On page 10-26, under "Slave Mode Operation", step 3 needs to be reworded to "Once the /SPISS falling edge is detected, the slave starts shifting data out on MISO and in from MOSI on SCK edges, depending on the states of CPHA and CPOL."


  • On page 10-26, step 5 needs to be modified: Delete the word "active" from "active SCK clock edge".


  • On page 10-35 and 10-36, under the "Slave Mode DMA Operation" section, step 3 needs to be modified in two places: Delete the word "active" from "active SCK edges" in the 1st sentence of the 1st paragraph and in the 4th sentence of the 2nd paragraph.


  • On page 10-36 , still under the "Slave Mode DMA Operation" section, step 4 needs to be modified in two places: Delete "active" from "active SCK edges" in the last sentence of both paragraphs.

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Chapter:  10 Page: 32
Reference Number: 35469
Change
Change the information bullet text from:
When the SPIF bit subsequently goes low, the last word has been transferred and the SPI can be disabled or enabled for another mode.

Change to:
When the SPIF bit subsequently gets set, the last word has been transferred and the SPI can be disabled or enabled for another mode.

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Chapter:  10 Page: 38
Reference Number: 39579
Change
In figure 10-13 (SPI Timing), place an overbar on the signal name PIO_NSPISSIN in the timing diagram.

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Chapter:  11 Page: 6
Reference Number: 36042
Change
In Table 11-2, the first two elements in the "Output from PPI" column of the row with DLEN > 8 bits, PACK_EN = 0, and DMA32 = 1 has incorrect data (the first two elements are nibble-reversed). Change from:
0x1122, 0x3344, 0x6655, 0x8877, 0xAA99, 0xCCBB, 0xEEDD, 0x11FF

Change to:
0x2211, 0x4433, 0x6655, 0x8877, 0xAA99, 0xCCBB, 0xEEDD, 0x11FF

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Chapter:  12 Page: 47
Reference Number: 36283
Change
In the second paragraph on the page, the description of the LFRS bit---though technically correct---is not worded clearly. Change from:
The LRFS bit determines the polarity of the frame sync pin that is considered a 'right' channel. Thus, setting LRFS = 0 indicates that a low signal on the RFS or TFS pin is the left channel. This is the default setting.

Change to:
The LRFS bit determines the polarity of the RFS or TFS frame sync pin for the channel that is considered a 'right' channel. Thus, setting LRFS = 0 (meaning that it is an active high signal) indicates that the frame sync is high for the 'right' channel, thus implying that it is low for the 'left' channel. This is the default setting.

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Chapter:  15 Page: 5
Reference Number: 34748
Change
The first paragraph of the "Timer Disable (TMRSy_DISABLE) Registers" section, indicates an incorrect value for the register bits.

Change from (bold text):
The Timer Disable registers allow 8 or 4 timers, for y = 8 or 4 respectively, to be disabled simultaneously. For each timer there is a single W1C control bit. Writing a 1 disables the corresponding timer; writing a 0 has no effect. The twelve bits can be cleared individually or in any combination. A read of the Timer Disable registers shows the status of the disable for the corresponding timer. A "1" indicates that the timer is disabled. All unused bits return 0 when read.

Change to (bold text):
The Timer Disable registers allow 8 or 4 timers, for y = 8 or 4 respectively, to be disabled simultaneously. For each timer there is a single W1C control bit. Writing a 1 disables the corresponding timer; writing a 0 has no effect. The twelve bits can be cleared individually or in any combination. A read of the Timer Disable registers shows the status of the disable for the corresponding timer. A "0" indicates that the timer is disabled. All unused bits return 0 when read.

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Chapter:  15 Page: 48
Reference Number: 40015
Change
Add the following information bullet in the TCNTL Register section:
Note: The TINT bit in the TCNTL register indicates that an interrupt has been generated. Note that this is not a W1C bit. Write a 0 to clear it. However, the write is optional. It is not required to clear interrupt requests. The core time module doesn’t provide any further interrupt enable bit. When the timer is enabled, interrupts can be masked in the CEC controller.

Also, in figure 15-28 (Core Timer Control Register) on page 15-49, the bit TINT bit description must change from:
TINT - W1C

Change to:
TINT - W0C

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Chapter:  16 Page: 37
Reference Number: 39910
Change
In figure 16-11 (SDRAM Memory Global Control Register), change the name of bit 31 from WIDTH to X16DE.

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Chapter:  17 Page: 2
Reference Number: 34645
Change
There are a series of errors in the "Booting the Processor" section's figures, regarding connecting the ADSP-BF561 processor to FLASH memory. The following changes are needed:
  • In figure 17-1 (Interface to 8-bit SRAM or Flash), change the AMS[X] pin name in the PROCESSOR block to AMS0.
  • In figure 17-2 (Interface to 16-bit SRAM or Flash), change the AMS[X] pin name in the PROCESSOR block to AMS0.
  • In figure 17-4 (ADSP-BF561 to ST FLASH), change the ARE pin name in the ADSP-BF561 block to AMS0.

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Chapter:  18 Page: 23
Reference Number: 35349
Change
The CYCLES and CYCLES2 registers are described as being read-only in User Mode, which is not correct. These registers are always read-write, regardless of User, Supervisor, or Emulator mode. Delete the following sentence (immediately beneath the i-bullet):
In User mode, these two registers may be read, but not written. In Supervisor and Emulator modes, they are read/write registers.

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Last Updated: March 10, 2009