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G.729AB VOICE CODEC

ITU-T Recommendation G.729 describes a voice compression algorithm based on Conjugate-Structure Algebraic-Code-Excited Linear Prediction (CS-ACELP). Annex A describes a reduced complexity version which is bit-stream interoperable with the full version of G.729. Annex B describes a silence compression scheme that includes Voice Activity Detection (VAD), Discontinuous Transmission (DTX) and ...More

G.729AB VOICE CODEC

Product Description

ITU-T Recommendation G.729 describes a voice compression algorithm based on Conjugate-Structure Algebraic-Code-Excited Linear Prediction (CS-ACELP). Annex A describes a reduced complexity version which is bit-stream interoperable with the full version of G.729. Annex B describes a silence compression scheme that includes Voice Activity Detection (VAD), Discontinuous Transmission (DTX) and Comfort Noise Generator (CNG) algorithms. G.729 is widely used as one of the key software components for packet based voice devices such as VoIP phones and private branch exchanges.

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EVALUATION BOARDS & DEVELOPMENT KITS

Features

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Functions

  • Conformance Standard: ITU-T G.729A Annex B
  • Target Processor: Code compatible across the Blackfin processor family ADSP-BF5xx.
  • Framework dependencies: None. No dependencies on processor peripherals or registers.
  • Release format: Object code module with C source wrapper.
  • Input format: Mono channel, non-interleaved buffer.
    • Encoder: signed 16-bits little-endian PCM samples.
    • Decoder: 16 bit per bit of unpacked bit stream or, 1 bit per bit of packed bit stream.
  • Output format: Mono channel, non-interleaved buffer.
    • Decoder: Signed 16-bits little-endian PCM samples.
    • Encoder: 16 bit per bit of unpacked bit stream or, 1 bit per bit of packed bit stream.
  • Input and output buffer samples per frame:
    • 160 bytes for PCM buffers
    • 164 bytes for unpacked bit stream buffers or, 14 bytes for packed bit stream buffers.
  • Sample Rate: 8 kHz
  • Bit rate: 8 kbit/s
  • Multi-channel: Fully re-entrant and multi-instancing capable.

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Performance Metrics

MIPS summary:

Code RAM (KiB) Data RAM (KiB) Constant Data Tables (KiB) MIPS
BF537 BF548 BF527
Average Peak Average Peak Average Peak
29.3 6.8 6.1 6.77 6.97 6.77 6.97 6.77 6.97
  • This table highlights example Blackfin processors and expected MIPS performance.
  • MIPS measured using typical bit rates 8 kbit/s, Fs = 8 kHz, optimal memory layout with code and data in L1 memory, worst case test vector, mono channel.
  • Both instruction and Bank A data cache have been enabled and data cache was set to write-back mode.
  • "Data RAM" refers to a single instance and includes stack, scratch and instance/state memory as well as minimum-size input and output single buffers.
  • 1 KiB = 1024 Bytes.

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Applications

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Requirements

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Availability and Licensing

Each module supports the Analog Devices, Inc. (ADI) Blackfin Processor family and is a licensed product that is available in object code format. Recipients must sign a license agreement with ADI prior to being shipped the modules identified in the license agreement.

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